Multifunction video compression circuit

Television – Bandwidth reduction system – Data rate reduction

Reexamination Certificate

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Details

C348S236000, C375S240230

Reexamination Certificate

active

06323904

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to video compression and, in the most important example, to MPEG2 coders, decoders and the like.
BACKGROUND ART
With the general acceptance of MPEG2 as a standard for the digital compression of video signals, many groups world-wide have developed or are developing coders or decoders; chip-sets are now commercially available and others have been announced. It is generally found, however, that existing circuit designs are inflexible and are directed only towards the requirements for standard definition television, typically main profile at main level.
It is an object of the present invention, to provide circuits—suitable for integration—which are flexible and which offer compatibility with higher profiles and levels of MPEG.
It is an object of certain aspects of the present invention to provide circuits—suitable for integration—which offer compact implementation of functions that cannot be implemented with existing coding and decoding chips or chip—sets.
It is still a further object of aspects of the present invention to provide circuit designs—suitable for integration—which can be used to implement in a cascadable form, functions including not only coding and decoding but also bitstream switching and editing.
It is explained in WO-A-9535628 that an information signal can with great advantage be provided from (for example) a decoder to a re-coder or other processing element downstream in the signal chain. The information bus may contain motion vectors and MPEG coding decisions which can be employed in re-encoding or later processing. The same disclosure introduces the concept of a coefficient domain which is the result of partial decoding of a compressed signal. It is found that certain functions, which would otherwise require decoding, processing and re-encoding, can be conducted more efficiently and with less errors in this coefficient domain.
It is a further object of the present invention to provide circuit designs suitable for integration—which take advantage of various features disclosed in WO-A-9535628.
BRIEF SUMMARY OF THE INVENTION
Accordingly, the present invention consists in a multi-function circuit for use with compressed video signals, comprising a variable length decoder having an elementary stream input, an information bus output and a quantised coefficient stream output; a variable length coder having an information bus input, a quantised coefficient stream input and an elementary stream output; a decoder comprising an inverse quantiser and an inverse transform; a coder comprising a quantiser and a transform; first routing means capable of routing an information bus signal to the variable length coder, and as a control to the decoder and to the coder; and second routing means capable of routing signals through the coder and the decoder and to the variable length coder.
In one form of the invention, two like circuits are combined to receive respective different layers of a compressed bitstream.


REFERENCES:
patent: 5138455 (1992-08-01), Greene
patent: 5280345 (1994-01-01), Uehara et al.
patent: 5319458 (1994-06-01), Shin
patent: 5754235 (1998-05-01), Urano
patent: 5764286 (1998-06-01), Kawamura et al.
patent: 5838377 (1998-11-01), Greene
patent: 0 627 858 A2 (1994-12-01), None
patent: 0 627 858 (1994-12-01), None
patent: 0 637 893 A1 (1995-02-01), None
patent: 0 637 893 (1995-02-01), None
patent: 0 696 873 (1996-02-01), None
patent: 0 696 873 A2 (1996-02-01), None
patent: WO 95 35628 (1995-12-01), None
patent: WO 9535628 (1995-12-01), None
“Cheops: a modular processor for scalable video coding,” V.M. Bove, et al. Visual Communications and Image Processing'91: Visual Communication, Boston, Nov. 11, 1991, pp. 886-893.
“FA 17.4: A single Chip Videophone Video Encoder/Decoder,” M. Harrand, et al. IEEE International Solid State Circuits Conference, col. 38, Feb. 1, 1995, pp. 292, 293, 382.
“A Programmable Solution for Standard Video Compression,” J. Fandrianto, et al. Institute of Electrical and Electronics Engineers, Feb. 24, 1999, pp. 47-50.
“A Multi-Standard Video Codec Architecture For the ISA/VL Bus,” D. Fairfield. Proceedings of the International Conference on Signal Processing Applications and Technology, vol. 2, Oct. 18, 1994, pp. 1173-1178.
“A Multi-Standard Video CODEC Architecture for the ISA/VL Bus”, D. J. Fairfield. Proceedings of the International Conference on Signal Processing Application and Technology, vol. 2, Oct. 18, 1994, pp. 1173-1178.
“A Programmable Solution for Standard Video Compression”, J. Fandrianto, et al. Intellectual Leverage, San Francisco, Feb. 24-28, 1992, No. Conf. 37, Feb. 24, 1992, Institute of Electrical and Electronics Engineers, pp. 47-50.
“FA 17.4: A Single Chip Videophone Video Encoder/Decoder”, IEEE International Solid State Circuits Conference, vol. 38, Feb. 1, 1995, pp. 292/293, 382.
“Cheops: A Modular Processor for Scalable Video Coding”, V. M. Bove, et al. Visual Communication and Image Processing ′91: Visual Communication, Boston, Nov. 11-13, 1991, vol. 1605 p. 02 of 2, Nov. 11, 1991.

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