Oscillators – Ring oscillators
Reexamination Certificate
2000-05-16
2001-09-11
Mis, David (Department: 2817)
Oscillators
Ring oscillators
C331S034000, C331S060000, C331S074000, C331S17700V, C331S185000
Reexamination Certificate
active
06288616
ABSTRACT:
The present invention relates to an oscillator circuit provided with delay cells having supply voltage terminals and being interconnected in a ring for providing an oscillator signal.
The present invention also relates to a voltage controlled oscillator (VCO), a phase locked loop (PLL), an integrated circuit (IC), and a telecommunication device, as outlined in the claims
6
,
7
,
8
and
9
respectively.
DE-OS-3634594 discloses a multifrequency oscillator shown in
FIG. 1
thereof, providing a first oscillator signal f (
0
), whereas additional oscillator signal frequencies (f) are being derived by means of a controllable switch from taps interconnecting delay cells arranged in a ring. Such an extensive oscillator is relatively slow, consumes a lot of power, and is not suited for very high frequency telecommunication applications.
An oscillator circuit acknowledged in the preambles of the aforementioned claims is disclosed in U.S. Pat. No. 5,844,447. The known oscillator circuit includes a first ring oscillator having inverters coupled to a first buffer, and a second ring oscillator having delay cells coupled to a second buffer. Each delay cell consists of a PMOS transistor and an NMOS transistor which are easy to be fully integrated on a chip. The first buffer output produces a first waveform having a high frequency and the second buffer output produces a second waveform having a lower frequency. It is generally known that the maximum achievable frequency of a ring oscillator is inversely proportional to the number of delay cells therein. This however restricts the application capabilities of a ring oscillator having several of such delay cells for use in the GHz range, such as common in nowadays telecommunication devices, in particular mobile telephones, pagers etcetera. In addition power consumption of these devices increases with an increasing user frequency. Therefore these known ring type oscillators circuits are less suitable for use in very high frequency range circuitry.
However it is an object of the present invention to provide a cost effective oscillator circuit which is simple, easy to be integrated on a small chip area, suitable for application in the GHz range, but nevertheless has a very low power consumption.
Thereto the oscillator circuit of the present invention is characterized in that the delay cells have supply voltage terminals in common, which terminals are coupled to the supply through coupling means for providing a further oscillator signal derived from the respective common supply voltage terminals.
It is an advantage of the present invention that the oscillator circuit operates at the relatively low frequency of the oscillator signal, whereas the further oscillator signal frequency is synthesized to be higher. However the lower operating frequency determines the lowered power consumption, which is especially important for mobile equipment and communication appliances. In practice a very low current consumption could be combined with a supply voltage of only a few volts. It should be noted that contrary to the conventional way of thinking the approach presented starts from the notion that, if at first the low frequency oscillator signal is being generated the further high frequency oscillator signal is acquired for free without requiring power or substantial hardware. A variety of coupling means may are applicable for the man skilled in the art. The coupling means may for example contain: a current source, a current measuring or converting device, one or more current mirrors or an impedance element, which in the most simple case is a resistor.
In addition the oscillator circuit of the invention is even capable of providing two oscillator signals simultaneously, which signals also have different frequencies. This simplifies the circuitry, reduces the necessary IC chip area and makes the circuit particularly but not necessarily exclusively useful for application in multistage—possibly double balanced—mixer circuits, such as in heterodyne transmitters, receivers and/or transceivers, like for GSM, Dect or pagers. Moreover the inventor established to compose an oscillator circuit, where the maximum achievable frequency fmax of the further oscillator signal does no longer (inversely proportional) depend on the number N of delay cells applied in the circuit as noted earlier. In fact fmax is made even fully independent from N. Besides it is noted that each of the oscillator signals is highly sinusoidal, and that consequently the power supply is not loaded with supply spikes, resulting in a stabile and static-free operation of the novel and inventive oscillator circuit.
An embodiment of the oscillator circuit of the present invention is characterized in that the even numbered delay cells are coupled to the one common supply voltage terminal, whereas the odd numbered delay cells are coupled to the other common supply voltage terminal. Advantageously the relation f
1
=N×f
2
holds for the oscillator circuit of the invention, wherein f
1
is the frequency of the high frequency further oscillator signal and f
2
is the frequency of the low frequency oscillator signal. In practice N will be even, that is 2, 4, 6, 8 . . . resulting in reliable integer values of possible frequency ratios, fully controlled by the number N of delay cells and suitable for a variety of applications and frequencies. If N increases the frequency difference between both oscillator signals increases, such that a higher achievable first oscillator frequency is being combined with a lowered power consumption because the power consumption is determined by the lower second oscillator frequency.
Another embodiment of the oscillator circuit according to the invention is characterized in that the number N of delay cells is even and is equal or larger than 4. Advantageously two oscillator frequencies are available simultaneously with f
1
=N×f
2
, whereas the oscillator signal having frequency f
1
is available in differential form and the oscillator signal having frequency f
2
is even available in quadrature form.
A further embodiment of the oscillator circuit according to the invention is characterized in that if each delay cell has a propagation delay &dgr;, it holds for the further oscillator signal frequency f
1
that it equals 1/(2&dgr;). Such an embodiment with preferably identical delay cells is particularly easy to integrate and may provide a very high frequency f
1
if &dgr; is made very small.
In its simplest embodiment a delay cell is an inverter, in particular a digital inverter, such that the low frequency oscillator signal is available in quadrature form, if N=4, 8 . . . , which is particular suited for heterodyne transmitters/receivers with digital modulation.
Of the possible technologies for implementing the oscillator circuit according to the invention on a chip IC area, such as GaAs or bipolar, CMOS has proven to be the most cost effective process.
REFERENCES:
patent: 2642526 (1953-06-01), Gallay
patent: 5262735 (1993-11-01), Hashimoto et al.
patent: 5844447 (1998-12-01), Choi
patent: 3634594A1 (1988-04-01), None
By Sugimoto Y. et al.: Entitled: “Study of Low Voltage, Low Power and High Frequency CMOS VCO Circuit”, IEICE Transactions of Fundamentals on Electronics, Communications and Computer Sciences, JP, Institute of Electronics Information and Comm. Eng. Tokyo vol. E79-A, No. 5 May 1, 1996 pp. 630-633.
By Sugimoto Y. et al: Entitled “Design of a Low-Voltage Low Power High-Frequency CMOS Current-Mode VCO Circuit by Using 0.6 MUM MOS Devices”, IEICE Transactions of Fundamental of Electronics, Communications and Computer Sciences, JP, Institute of Electronics Information and Comm. Eng. Tokyo, vol. E80-A, No. 2, Feb. 1, 1997, pp. 304-311.
Mis David
U.S. Philips Corporation
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