Multiframe-structured bit synchronization circuit for data signa

Pulse or digital communications – Synchronizers – Synchronization failure prevention

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Details

370503, 370510, 371 471, 371 671, G11B 1722

Patent

active

058223827

ABSTRACT:
The bit synchronization circuit of the present invention has an extraction circuit for extracting only bits at specified positions from each frame of a data signal comprising a plurality of frames including synchronization detection bits which are set to specified positions of each frame and whose values are different between adjacent frames. It is decided whether synchronization is established or not by a synchronization decision circuit in accordance with values of the bits extracted from adjacent frames among the extracted bits. In the case of the above decision, the bits extracted from the adjacent frames are compared each other among the extracted bits and it is decided that synchronization is established only when the above comparison results do not coincide with each other N times consecutively. Moreover, it is decided that synchronization is not established only when the comparison results do not coincide with each other N times consecutively.

REFERENCES:
patent: 4811367 (1989-03-01), Tajika
patent: 4876701 (1989-10-01), Sanner
patent: 5107495 (1992-04-01), Kamoi et al.
patent: 5259004 (1993-11-01), Nakayama
patent: 5363438 (1994-11-01), Tanaka

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