Multidrop analog signal bus

Multiplex communications – Channel assignment techniques – Using a separate control line or bus for access control

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Details

370532, 34082552, H04Q 1100

Patent

active

061222844

ABSTRACT:
In the preferred embodiment, the outputs of a plurality of analog signal generators are connected to a single wire (the analog bus). Each analog signal generator is addressable by a unique code provided to its respective address input terminals. A host controller selectively addresses only one of the analog signal generators such that an output of only one of the analog signal generators is applied to the analog bus at a time. In this manner, a single wire may be used to transmit a plurality of analog signals to a receiver. In one embodiment, the receiver is a MUX having an output connected to an ADC.

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