Static information storage and retrieval – Format or disposition of elements
Reexamination Certificate
2001-03-22
2002-07-23
Elms, Richard (Department: 2824)
Static information storage and retrieval
Format or disposition of elements
C365S230010, C365S230020
Reexamination Certificate
active
06424553
ABSTRACT:
FIELD OF THE INVENTION
The present invention concerns a means for providing addressability in an apparatus comprising one or more volume elements, wherein said volume or volume elements together with said means form a part of a two- or three-dimensional matrix in said apparatus, wherein a volume element comprises one or more cells having a data storage, data-processing or signal-processing functionality depending on the electronic or electric properties of a material of said volume element, wherein said means provides addressability to a specific location in a volume element by establishing a selective electrical connection to said volume element or in case said volume element comprises more than one cell, a specific cell thereof, wherein the selection of a specific volume element or cell thereof takes place by a providing a not necessarily simultaneous electrical connection to three or more electrodes formed by said means and contacting said volume element for effecting a selective interaction therewith in a region thereof in close proximity to said electrodes, and wherein said region defines a cell in said volume element thus interacted upon.
The present invention also concerns an apparatus comprising such means wherein the means together with one or more volume elements form a part of a two- or three-dimensional matrix in said apparatus, wherein a volume element comprises one or more cells having a data storage, data-processing or signal-processing functionality depending on the electronic or electric properties of a material of said volume element, and wherein the apparatus comprises more than one matrix of this kind.
Generally the present invention discloses addressing architectures that provide electronic N-terminal access to volume elements or regions thereof in two- or three-dimensional matrix structures, where the number N of terminals to be connected at each address in the matrix is at least three.
BACKGROUND OF THE INVENTION
Orthogonal addressing matrices in two dimensions are employed extensively in a wide variety of electronic devices such as cameras, memory devices and displays where it is required to have unique electronic access to each individual matrix element.
The simplest type of matrices consists of one set of mutually parallel electrode lines (termed “a” electrodes below) in one plane, located in proximity to another parallel plane containing another set of mutually parallel electrode lines (termed “b” electrodes below). The “a” and “b” set of electrodes are oriented so as to cross each other, typically in orthogonal fashion, providing addressability to the volume elements between the crossing electrodes. Thus, the volume element between electrode a
i
in the “a” electrode set and electrode b
j
in the “b” electrode set can be acted upon electrically by connecting the electrodes a
i
and b
j
to an appropriate source of current or voltage. The volume elements can accommodate active circuit elements capable of being triggered by an input signal, or in themselves be provided as switching or as passive elements, a physical state of which may be altered by applying an input signal or detected upon addressing in the “a” and the “b” electrodes, then being capable of realizing memory elements for storing binary or multilevel logical values.
A device based on matrices of this kind are e.g. disclosed in International patent application No. PCT/NO98/00185 (U.S. Pat. No. 6,055,180), assigned to the present applicant. This concerns an electrically addressable passive device which can be used in optical detector means, volumetric data storage devices or data processing devices. The disclosed device comprises a functional medium in the form of a continuous or patterned structure which may undergo a physical or chemical change of state. This functional medium which corresponds to the volume element or the present invention, comprises individually addressable cells provided between the anode and cathode in an electrode means which contacts the functional medium in the cell and causes an electrical coupling thereto. The anodes are provided as a first set parallel stripe-like electrodes in a layer contacting the functional medium on one side and the cathodes are provided as a second set of stripe-like electrodes that contacts the functional medium on the other side, the stripe-like electrodes in each set being mutually parallel and each electrode set being oriented such that the electrodes therein in one are oriented orthogonal with respect to the electrodes in the other. In practice a cell in the volume element of the functional medium is now defined at the crossing of a stripe-like electrode of the first set with a stripe-like electrode of the second set. When a cell in this device is addressed, e.g. for writing, reading or switching of e.g. a logical value assigned to a cell, electric energy is applied directly to the functional medium of the cell via a selected pair of crossing electrodes in respectively the first and the second set.
International patent application No. PCT/NO98/00212, likewise assigned to the present applicant discloses, a similar device, wherein, however, the electrode matrix is provided with the electrode set mutually isolated in a bridge arrangement and the functional medium provided over and covering the electrode sets. In addition to its possible use as an electrical addressable memory device, this particular arrangement with bridged electrodes covered by the functional medium, as opposed to the above-mentioned device wherein the functional medium is provided in sandwich between the electrodes, facilitates its use in for instance in an optical or electronic camera or in a chemical camera or in an electrically addressable display device.
Finally International patent application PCT/NO98/00237, also assigned to the present applicant, discloses a ferroelectric device for processing and/or storage of data with passive electrical addressing of the functional medium which is a thin film of ferroelectric material provided over and covering the electrode sets which also here are provided in a bridged arrangement.
In all the above-mentioned devices the functional medium corresponding to a volume element provided between or over the electrode sets can be deposited as a global layer, in which the individual cells of course, always will be defined by the crossings between electrodes in the first and second electrode set respectively. However, the functional medium forming the element may also be patterned or pixelated such that individual volume elements is provided between or over the crossing of the electrodes in the respective sets, thereby forming a volume element comprising only one cell. This, of course, does not affect the total possible number of cells in the matrix, as this essentially will be the product of the number of electrodes in each set.
In arrays and matrices of the above-mentioned kind that store or process electrical signals the matrix or array elements thus defined may include various kind of components and circuitry, depending on the application, but at each crossing point only two independent electrical connections to the outside world is possible. Thus, the two sets of electrodes can only support exclusive addressing to two terminal devices or circuits, due to the two dimensions available.
Several approaches are used today in electronic systems based on matrices and where each matrix element requires more than two terminal connections. In SRAM technology the memory cells require more than two terminals, i.e. Vcc, bit, −bit and word. A prior art matrix solution for addressing the memory cells in SRAM technology is shown in FIG.
1
and uses two parallel lines, Vcc line and word line, oriented perpendicular to two other parallel lines, −bit and bit lines. No exclusive addressing can be obtained between the two parallel lines, i.e. no exclusive addressing between −bit and bit for instance.
Another prior art solution for realizing exclusive addressing between more than two lines (or electrodes) is shown in FIG.
2
. Her
Berggren Rolf Magnus
Leistad Geirr Ivarsson
Nordal Per-Erik
Elms Richard
Jacobson & Holman PLLC
Nguyen Van-Thu
Thin Film Electronics ASA
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