Multideposition SACVD reactor

Details Multideposition SACVD reactor Multideposition SACVD reactor

2001-07-12

2004-08-03

Hassanzadeh, Parviz (Department: 1763)

Coating apparatus

Gas or vapor deposition

Multizone chamber

C118S728000, C156S345330, C156S345340, C156S345290

Reexamination Certificate

active

06770144

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the manufacture of semiconductor integrated circuits (ICs) and more particularly to a multideposition sub-atmospheric chemical vapor deposition (SACVD) reactor enabling the rapid thermal deposition of dielectric materials such Si
3
N
4
, SiO
2
, and SiON and of non-dielectric materials such as polysilicon onto a substrate. According to the present invention, said dielectric
on-dielectric materials can be now deposited according to the desired sequence in the same chamber of the multideposition SACVD reactor, significantly reducing cycle time, total thermal budget and pattern factor effects.
BACKGROUND OF THE INVENTION
Short cycle time and low thermal budget are certainly the most critical points for Application Specific Integrated Circuit (ASIC) and Dynamic Random Access Memory (DRAM) products manufacturing respectively. The continuous technical progress in the last decades has resulted in the emergence of new techniques to improve product integration and speed that shows out the necessity to work deeper on deposition tool to improve their characteristics. Requirements such as low thermal budget, low pattern factor, foreign element control and short cycle time are now becoming of paramount importance. A low thermal budget is essential to keep IGFET effective channel length (L
eff
) within specifications, to increase the process window and to have low junction contact resistance. Another important parameter is the pattern factor which is determining to embed memory cells in a logic chip. Still another parameter (previously deemed more secondary) is the foreign element control. Foreign elements that are incorporated into the deposited films during fabrication also drive device performance, and thus are becoming more important to date, as devices become more and more dense and complex. The possibility to control foreign element presence in deposited films facilitates the tuning of the devices and the correction or adjustment of some electrical fails such as junction leakages and the retention time. Finally, short cycle times which increase the manufacturing throughput are also worthwhile in terms of cost reduction. All these parameters have become critical in semiconductor devices particularly when it is required to deposit dielectric and non-dielectric materials in sequence according to the Chemical Vapor Deposition (CVD) technique. It would be highly desirable to perform the maximum deposition steps in the same equipment without unloading the wafers in order to improve the manufacturing throughput and to reduce the cycle time.
In the course of fabricating IGFETs for a standard DRAM product, at the stage of the gate conductor formation, it is required to form a stack (GC stack) comprised of a bottom 10 nm thick SiO
2
gate layer, then a 80 nm thick doped polysilicon layer, a 70 nm thick tungsten silicide (WSi
x
) layer and finally a 180 nm thick top protective cap Si
3
N
4
layer. Next, the GC stack is patterned by dry etching to produce the gate conductor lines (GC lines) and a thin SiO
2
spacer is formed by thermal oxidation on the exposed sidewalls of the doped polysilicon material. All these processing steps are performed in a different tool in the so-called Middle End Of the Line (MEOL) module.
For instance, the thin SiO
2
bottom gate layer is obtained by thermal oxidation using an Atmospheric Pressure Oxidation furnace (APOX) as standard, such as the SVG VTR 7000 (oxidation) vertical furnace sold by SVG-THERMCO, San Jose, Calif., USA. The deposition of the 80 nm thick doped polysilicon layer and the 70 nm thick WSi
x
layer is performed in two different chambers of a SACVD Centura HTF reactor, a tool manufactured by Applied Materials Inc, Santa Clara, Calif., USA using the following operating conditions:
Doped Polysilicon Deposition
Pressure:
80 Torr
Temperature:
660° C.
SiH
4
flow:
0.3 slm
PH
3
flow:
0.09 slm
H
2
flow:
9.9 slm
Dep. rate:
80 nm/min
wherein “sccm” denotes standard cubic centimers per minute and “slm” denotes standard liters per minute.
WSi
x
Deposition
Pressure:
1 Torr
Temperature:
550° C.
WF
6
flow:
2.4 sccm
SiH
2
Cl
2
flow:
175 sccm
Ar flow:
1500 sccm
Dep. rate:
12 nm/min
Finally, the Si
3
N
4
material is deposited in a LPCVD batch furnace, such as a TEL Alpha 8s, a tool sold by TOKYO ELECTRON Ltd, Tokyo, Japan using the operating conditions recited below.
Si
3
N
4
Deposition
Step 1
Pressure:
150 mTorr
Temperature:
715° C.
NH
3
flow:
250 sccm
DCS flow:
50 sccm
Wafer spacing:
0.2 inch
Dep. rate:
0.7 nm/min
Dep. time:
40 min
Step 2
Pressure:
80 mTorr
Temperature:
770° C.
NH
3
flow:
400 sccm
DCS flow:
80 sccm
Wafer spacing:
0.2 inch
Dep. rate:
1.5 nm/min
Dep. time:
120 min
The first step must be conducted at a low temperature to prevent WSi
x
oxidation at boat insertion in the furnace. About 100 wafers are processed for a total time (including loading/unloading operations) of about 375 min.
TABLE I below summarizes this sequence of deposition steps that are performed in the MEOL module.
TABLE I
Materials
Deposition process
SiO
2
APOX
Doped polysilicon
SACVD (chamber 1)
WSi
x
SACVD (chamber 2)
Si
3
N
4
LPCVD
More generally, if we consider all processing steps that are performed in the DRAM manufacturing line, the use of LPCVD and APOX furnaces are substantially limited to the Front End Of the Line (FEOL) and MEOL modules, as summarized in TABLE II below, for the deposition for different types of materials.
TABLE II
Modules
FEOL
MEOL
Temp.
600-950° C.
550-750° C.
Time
3-7 H
3-7 H(1); 5 min(2)
Si
3
N
4
LPCVD
LPCVD (1)
SiON
LPCVD
LPCVD (1)
SiO
2
APOX
APOX (1)
Polysil
LPCVD
SACVD (2)
WSi
x
SACVD (2)
(1) and (2) respectively refer to the duration for LPCVD/APOX and SACVD processes. There is no breakdown when the wafer is moved from chamber
1
to chamber
2
of the SACVD tool but there is a significant breakdown after the wafer is unloaded from chamber
2
to be loaded in the LPCVD furnace. Because, the LPCVD tool is of the batch type, there is an important wait time before a full batch of 100 wafers is loaded. As a consequence, before inserting the boat in the furnace, the wafers need to be cleaned for instance in a FSI spray tool (FLUOROWARE SYSTEMS Inc., Minneapolis, USA) using a SP/Huang AB cleaning sequence. As a whole, these operations are time consuming.
It is not possible to deposit the Si
3
N
4
material in the same AME Centura reactor because processing chambers are strictly limited to the deposition of polysilicon films or WSi
x
films.
Applicants have discovered a manner to modify this conventional SACVD reactor normally exclusively used to perform polysilicon deposition to add the capacity of depositing dielectric materials such as Si
3
N
4
, SiON and SiO
2
in addition to polysilicon. As a result, multideposition of materials as different as dielectric and polysilicon in the reactor chamber according to any desired sequence is now possible without the above mentioned inconveniences (wait time, cleaning and long cycle time).
SUMMARY OF THE INVENTION
It is therefore a primary object of the present invention to provide a multideposition CVD reactor enabling the rapid thermal deposition of dielectric materials such as Si
3
N
4
, SiO
2
, and SiON and non-dielectric materials such as polysilicon onto a substrate in the same chamber of the reactor.
It is another primary object of the present invention to provide a multideposition CVD reactor provided with multiple chambers enabling the rapid thermal deposition of dielectric materials such as Si
3
N
4
, SiO
2
, and SiON and non-dielectric materials such as polysilicon onto a substrate in two dedicated chambers of the reactor.
It is another object of the present invention to provide a multideposition CVD reactor enabling the rapid thermal deposition of dielectric materials such as Si
3
N
4
, SiO
2
, and SiON and non-dielectric materials such as polysilicon onto a substrate that is particularly adapted to ASIC production (short cycle times and low thermal budget).
It is another object of the present invention to provide a multide

Affiliated with

Also associated with

Rating

Multideposition SACVD reactor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multideposition SACVD reactor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multideposition SACVD reactor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3294336