1981-08-21
1984-05-01
Edlow, Martin H.
357 71, 357 80, H01L 2348, H01L 2302, H01L 3902
Patent
active
044464770
ABSTRACT:
A novel thin film processing substrate is embodied into a multichip hybrid module. The processing substrate is provided with conductive vias which are arranged in an area array having the same pattern as the lead out pin vias on a base substrate. The top surface of the processing substrate is built up by thin film techniques to provide a laminate thereon comprising a ground plane and a plurality of thin film X-direction and Y-direction signal distribution lines separated one from the other by thin polyimide insulating layers. The interconnecting thin film lines and polyimide layers are built up as patterns using photolithographic techniques. The X and Y-direction conductive lines and the ground plane are selectively interconnected through the vias and each other to form a predetermined signal distribution circuit. Terminal pads are provided on both the X and Y-direction lines to permit making electrical interconnections to the integrated circuit chips which are mounted on the processing substrate thus forming a circuit pattern between the integrated circuit chips and the lead out pins on the base substrate. Bumps are provided on the top of the vias in the base or pinned substrate for connecting it to the processing substrate after the integrated circuit chips have been mounted thereon.
REFERENCES:
patent: 4221047 (1980-09-01), Narken et al.
patent: 4322778 (1982-03-01), Barbour et al.
Honn, J. J., "Eighty Pin Package for Field Effect Transistor Chips", IBM Tech. Discl. Bull., vol. 15, No. 1, p. 308, Jun. 1982.
McIntosh et al., "Packaging of Integrated Circuits", IBM Tech. Discl. Bull., vol. 15, No. 6, pp. 1977-1979, Nov. 1972.
Currie Thomas P.
Goldberg Norman
Badgett J. L.
Edlow Martin H.
Scott T. J.
Sowell J. B.
Sperry Corporation
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