Multichip semiconductor small outline integrated circuit package

Details Multichip semiconductor small outline integrated circuit package Multichip semiconductor small outline integrated circuit package

1993-06-09

1994-08-09

Thompson, Gregory D.

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

361729, 361813, 437218, 437219, H05K 700

Patent

active

053372166

ABSTRACT:
A semiconductor package houses a plurality of single two terminal semiconductor components. The package is a plastic or ceramic small outline integrated circuit package and is adapted for surface mounting. Each semiconductor element is in a die form and one terminal is directly bonded to one of the external leads. The other terminal is bonded to a jumper that in turn is bonded to the other lead. The resultant package is encapsulated and the external leads are formed for surface mounting. V-shaped grooves formed on the top and bottom of the package separate each semiconductor component and provide a means to separate each or a combination of individual semiconductor components from the package by allowing them to be snapped apart at the V-groove. The resultant package has a very low profile that allows it to be used in thin profile, high density electronic assemblies.

REFERENCES:
patent: 3926746 (1975-12-01), Hargis

Affiliated with

Also associated with

Rating

Multichip semiconductor small outline integrated circuit package does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multichip semiconductor small outline integrated circuit package, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multichip semiconductor small outline integrated circuit package will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-220784