Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2002-07-08
2004-12-21
Thompson, Craig A. (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
Reexamination Certificate
active
06833626
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a chip-on-chip multichip module in which a plurality of chips are bonded to each other and a method for performing a connection test for the module.
Recently, a “single-chip system LSI”, that is, an LSI with a multiplicity of functions integrated together within a single chip, has been introduced and various design techniques have been proposed for the single-chip system LSI. In particular, an advantage of the single-chip system LSI is that a high-performance multifunction device is realized with a multiplicity of functions such as memories of, e.g., a dynamic random access memory (DRAM) and a static dynamic random access memory (SRAM) and circuits of, e.g., logic and analog circuits, integrated within a single semiconductor chip. However, in fabricating multiple devices on a single substrate, which require different manufacturing processes, many problems regarding costs and manufacturing techniques have to be overcome.
In order to solve these problems, a chip-on-chip system LSI formed by bonding multiple chips to each other was proposed as disclosed in Japanese Laid-Open Publication No. 58-922330. A chip-on-chip multichip module is formed as follows. Pad electrodes formed on the upper surface of a chip (i.e., a mother chip) functioning as a substrate, are connected, via bumps, to corresponding pad electrodes formed on the upper surfaces of chips-to-be-mounted (i.e., daughter chips), and the mother chip and the daughter chips are then bonded to each other. In this manner, the mother and daughter chips are electrically connected to each other, thereby forming the multichip module. Unlike the single-chip system LSI, multiple functions are separately integrated into the respective multiple chips in the chip-on-chip multichip module. Thus, the chips can have their size reduced and their yield increased. In addition, since the chip-on-chip multichip module can easily include devices that are different in type and process generation, the resultant device is easily implemented as a multifunction device. Furthermore, wiring length required for communication between the mother and daughter chips is very short in a system LSI utilizing the chip-on-chip multichip module, as compared to system LSIs utilizing other types of multichip modules. This allows high-speed communication, which is as fast as communication between blocks in the known single-chip system LSI.
As described above, the chip-on-chip multichip module is a very important technique replacing the known single-chip system LSI. However, an appropriate means for testing connections between the pads when the chips are bonded to each other has not yet been established.
Specifically, each of the mother and daughter chips includes a number of the pads used for sending and receiving signals and the mother chip pads and daughter chip pads are bonded to each other. Thus, required is a means with a simple structure for quick testing a very large number of the connections between the pads.
SUMMARY OF THE INVENTION
In view of the fact that an impedance value can be measured at a very high sensitivity in a structure where impedance elements are placed in parallel, the present invention is made for providing a chip-on-chip multichip module having a structure that allows a large number of connections between bond pads in the module to be tested in a quick and simple manner, and a method for performing such connection test for the module.
An inventive multichip module, which includes a plurality of chips each having a plurality of bond pads, and which is formed by electrically connecting the bond pads of one of the chips to the corresponding bond pads of another one of the chips, includes: a plurality of trunk wires; and a plurality of branch wires, which are connected to two of the trunk wires so as to be in parallel with each other. Each of the bond pads is connected to an associated one of the trunk wires via an associated one of the branch wires.
In the inventive module, where connections are made between the parallel-connected bond pads that are connected to one of the trunk wires and the corresponding parallel-connected bond pads connected to another one of the trunk wires, if any one of such electrical connections is poorly made, a current value flowing between the trunk wires is smaller than a current value supposed to be obtained where there is no poor connection. Thus, attainable is a multichip module with a structure that makes it possible to perform, in a simple and quick manner, a test for determining whether the connection between the bond pads is properly made or not when the chips are bonded to each other.
In one embodiment of the present invention, the inventive module may further include a plurality of connection control elements inserted in the respective branch wires.
In this particular embodiment, each of the connection control elements is a switching element or a rectifying element having a polarity by which the rectifying element is forward biased when a voltage is applied to the branch wires at a time of a connection test.
In one embodiment of the present invention, the chips include a first chip having a first set of bond pads, and a second chip having a second set of bond pads. The first and second sets of bond pads are electrically connected to each other. The trunk wires include a first trunk wire and a second trunk wire. The branch wires include a first set of branch wires branching off from the first trunk wire, and a second set of branch wires branching off from the second trunk wire. The bond pads of the first set are connected to the branch wires of the first set, respectively. The bond pads of the second set are connected to the branch wires of the second set, respectively. Then, it is possible to obtain a multichip module with a structure that allows connection between the two chips having their respective internal circuits to be easily tested.
In this particular embodiment, one set of the first and second sets of branch wires may extend into the first and second chips.
In another embodiment, the chips include: a first chip having a first set of bond pads; a second chip having a second set of bond pads; a third chip having a third set of bond pads, a fourth set of bond pads, and wires connecting the third and fourth sets of bond pads to each other. The bond pads of the first set are electrically connected to the respective bond pads of the third set, and the bond pads of the second set are electrically connected to the respective bond pads of the fourth set. The trunk wires include a first trunk wire and a second trunk wire. And the branch wires include: a first set of branch wires branching off from the first trunk wire and located between the first trunk wire and the bond pads of the first set, and a second set of branch wires branching off from the second trunk wire and located between the second trunk wire and the bond pads of the second set. In that case, it is possible to obtain a multichip module suitable for a case in which the third chip is used as a chip including only wires.
In another embodiment of the present invention, the chips include a first chip having a first set of bond pads, and a second chip having a second set of bond pads. The first and second sets of bond pads are electrically connected to each other. The trunk wires include a first trunk wire, a second trunk wire, and an intermediate trunk wire that is connected to the first and second trunk wires. The branch wires include: a first set of branch wires that extend from the first trunk wire so as to be in parallel with each other; a second set of branch wires that extend from the second trunk wire so as to be in parallel with each other; a first set of intermediate branch wires that extend from the intermediate trunk wire so as to be in parallel with each other and in series with the respective branch wires of the first set; and a second set of intermediate branch wires that extend from the intermediate trunk wire so as to be in parallel with each other and in series with t
Kajiwara Jun
Kinoshita Masayoshi
Sakiyama Shiro
Matsushita Electric Industrial. Co., Ltd.
McDermott Will & Emery LLP
Thompson Craig A.
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