Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2001-09-20
2003-10-07
Talbott, David L. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S784000, C257S786000, C257S723000
Reexamination Certificate
active
06630744
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to multichip modules that have stacked semiconductors, and, more particularly, to multichip modules that have stacked semiconductor chips including analog cells formed in lower chips.
Integrating a number of different circuits forms a multifunctional semiconductor integrated circuit. To further increase the functions of the semiconductor integrated circuit, a semiconductor chip (hereinafter referred to as a “stack chip”) is stacked on another semiconductor chip (hereinafter referred to as a “mother chip”). This circuit arrangement is referred to as a “multichip module”. More specifically, a plurality of chips with different functions are stacked to form the multichip module, thus reducing the surface area of the multichip module. This arrangement also reduces the number of the chips that are packaged on a substrate, thus lowering the manufacturing cost.
A conventional multichip module includes a mother chip and a stack chip. The mother chip has a computation circuit including analog and digital circuits and a control circuit for controlling an electronic device. The stack chip is stacked on the mother chip and functions as a dynamic random access memory (DRAM) for storing data for the control circuit.
Generally, the mother chip includes an analog cell and a digital cell. The analog cell generally refers to a circuit using analog signal data and includes, for example, a phase lock loop (PLL), an analog/digital converting circuit, a digital/analog converting circuit, and a phase comparison circuit. The digital cell generally refers to a circuit using digital signal data and includes a computation circuit including various logic circuits and a memory. Since the digital circuit operates in accordance with a digital signal, the circuit is relatively resistant to noise. Further, since the digital circuit is operable even if the signal is relatively weak, the operation speed of the circuit is increased and the power consumption is lowered. A general electronic device, such as a CD player and a display, is controlled by using an analog signal (for example, controlling motor torque of a CD player). Thus, a control circuit for controlling the electronic device receives an analog signal as an input signal and generates an analog signal as an output signal. More specifically, the control circuit receives the analog signal and converts the signal to a digital signal for various computation processes. After the processes, the control circuit converts the digital signal to an analog signal, or an output signal. Accordingly, the control circuit must be provided with a number of semiconductor chips that have both analog and digital circuits.
FIGS. 1A and 1B
are respectively a plan view and a cross-sectional view showing a prior art multichip module
100
. A mother chip
101
includes a substrate
102
and a circuit area
103
formed on the substrate
102
. The circuit area
103
includes analog cells
104
and a digital cell
105
. The digital cell
105
is separate from the analog cells
104
. An I/O cell area
106
is located at the periphery of the mother chip
101
and includes a plurality of input/output cells (I/O cells)
123
. A signal is transferred between each I/O cell
123
and an external device. In other words, the I/O cell area
106
is formed by a group of I/O cells
123
.
Each I/O cell
123
includes a wire connected to a certain circuit of a corresponding analog or digital cell
104
,
105
, a buffer transistor
107
, and a bonding pad
108
connected to the external device. The buffer transistor
107
amplifies (buffers) a relatively weak signal for an internal circuit of the mother chip
101
and protects the circuit from noise caused by external signals. The size of the buffer transistor
107
is extremely large, for example, several hundreds of times as large as that of a component of the circuit area
103
. The bonding pad
108
of each I/O cell
123
is an electrode with which the I/O cell
123
is wire-bonded with a lead frame (not shown). All signals transferred between the multichip module
100
and an external circuit pass through the I/O cell area
106
.
An insulating layer
109
is applied to the circuit area
103
. A stack chip
110
is mounted on the insulating layer
109
and includes bonding pads
111
. Each bonding pad
111
is connected to the corresponding bonding pad
108
of the I/O cell area
106
through a wire
112
. The stack chip
110
is thus connected to a certain circuit of the circuit area
103
.
For example, one of the analog cells
104
of
FIG. 2
receives a digital signal from the digital cell
105
and converts the signal to an analog signal (which indicates voltage or current). The analog cell
104
then sends the analog signal to an external device through the corresponding I/O cell
123
. Impedance between circuits and signal delay are adjusted such that the external device accurately receives the analog signal. Further, the length and the lateral dimension of each wire
124
,
126
are optimized for this purpose.
If any wire
112
of the stack chip
110
crosses the corresponding analog cell
104
or the corresponding wires
124
,
126
, noise due to the electric field generated by the wire
112
affects the analog cell
104
. This may hinder the operation of the analog cell
104
or change its characteristics. Normally, the stack chip
110
is connected to the digital cell
105
through the corresponding I/O cells
123
, the wires
112
, and wires
125
. Accordingly, noise caused by each wire
125
also affects the analog cell
104
.
As a result, the analog cells
104
of the multichip module
100
are separately located at corresponding corners of the circuit area
103
, as shown in FIG.
1
. This prevents the wires
112
from crossing the analog cells
104
or the wires
124
,
126
.
However, if the analog cells
104
must be located on the mother chip
101
to avoid interfering with the wires
112
, which connect the stack chip
110
to the I/O bus (the I/O cell area
106
), the design of the mother chip
101
becomes complicated. Particularly, if the circuit area
103
must receive a relatively large, inseparable analog cell, a multichip module becomes infeasible. Accordingly, there is a need for a simpler mother chip design.
Further, each bonding pad
111
of the stack chip
110
is normally connected to a certain circuit of the mother chip
101
and is not connected to an external circuit such as a power source through the corresponding bonding pad
108
. However, to prevent the wires
112
from interfering with one another, the wires
112
, which are connected to the corresponding bonding pads
108
in the I/O bus, must be separated from one another at substantially equal angular intervals. This increases the area of the I/O bus.
In addition, the I/O cell area
106
is formed at the periphery of the multichip module
100
to ensure a sufficient space for aligning the I/O cells
123
. It is thus impossible to reduce the I/O cell area
106
over a certain extent. Accordingly, even if the circuit area
103
is minimized, the area of the mother chip
101
cannot be reduced sufficiently.
BRIEF SUMMARY OF THE INVENTION
Accordingly, it is an objective of the present invention to provide a multichip module that is easy to design and has a reduced area.
To achieve the foregoing and other objectives and in accordance with the purpose of the present invention, the invention provides a multichip module that has first and second semiconductor chips. The first semiconductor chip has a circuit area and at least one bonding pad located in the circuit area. The second semiconductor chip is located on the first semiconductor chip and has at least one bonding pad that is wire-bonded with the bonding pad of the first chip.
The present invention includes a multichip module that has first and second semiconductor chips. The first semiconductor chip includes a circuit area and first and second I/O cell groups. The first I/O cell group is located outside the circuit area and has a plurality of I
Fish & Richardson P.C.
Sanyo Electric Co,. Ltd.
Talbott David L.
Thai Luan
LandOfFree
Multichip module does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multichip module, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multichip module will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3160121