Multichannel receiver circuit for parallel reception

Radiant energy – Photocells; circuits and apparatus – Photocell controlled circuit

Reexamination Certificate

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C327S319000, C327S321000, C359S199200, C330S12400D, C455S303000, C250S2140DC

Reexamination Certificate

active

06583400

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multichannel receiver circuit that suppresses effectively crosstalk (signal interference) between the channels. More particularly, the invention relates to a multichannel receiver circuit for receiving in parallel electrical input signals to produce electrical output signals by way of respective channels, in which each of the output signals has two different logic levels, such as logic high (H) and low (L) levels, according to the level of a corresponding one of the input signals.
2. Description of the Related Art
In recent years, with the development and advance of communications technology, there is the growing need to transmit data at a possibly high speed not only in trunk lines but also in or between communication devices (e.g., transmission terminals and exchanges), or computers. In the high-speed transmission systems of this type, the “parallel transmission” technique has been used, in which a high-speed signal is divided into rather low-speed signals and then, they are transmitted in parallel by way of multiple channels. “Multichannel receiver circuits” are used for receiving and amplifying these rather low-speed signals in parallel through multiple channels.
With the multichannel receiver circuits of this type, an electric input signal with a relatively small amplitude is typically amplified by a built-in amplifier circuit to thereby produce an electric output signal with a relatively large amplitude in each channel. In this case, usually, the amplification factor of the amplifier circuit is considerably large.
FIG. 1
schematically shows the configuration of an example of the prior-art multichannel receiver circuits of this type. The receiver circuit
101
in
FIG. 1
is formed and integrated on a semiconductor substrate
101
a
in the form of an Integrated Circuit (IC). The receiver circuit
101
comprises first to n-th sections with the same circuit configuration that constitute respectively the first to n-th channels, where n is an integer greater than unity.
In the first section for the first channel, an amplifier circuit
111
-
1
and an output buffer circuit
112
-
1
are provided. The amplifier circuit
111
-
1
receives a first input signal S
IN1
through the first input terminal of the receiver circuit
101
and produces a first amplified input signal S
INA1
. The output buffer circuit
112
-
1
receives the first amplified input signal S
INA1
from the circuit
111
-
1
and produces a first output signal S
OUT1
at the first output terminal of the circuit
101
.
In the second section for the second channel, an amplifier circuit
111
-
2
and an output buffer circuit
112
-
2
are provided. The amplifier circuit
112
-
2
receives a second input signal S
IN2
through the second input terminal of the receiver circuit
101
and produces a second amplified input signal S
INA2
. The output buffer circuit
112
-
2
receives the second amplified input signal S
INA2
from the circuit
111
-
2
and produces a second output signal S
OUT2
through the second output terminal of the circuit
101
.
Similarly, in the n-th section for the n-th channel, an amplifier circuit
111
-
n
and an output buffer circuit
112
-
n
are provided. The amplifier circuit
111
-
n
receives a n-th input signal S
INn
through the n-th input terminal of the receiver circuit
101
and produces a n-th amplified input signal S
INAn
. The output buffer circuit
112
-
n
receives the n-th amplified input signal S
INAn
from the circuit
111
-
n
and produces a n-th output signal S
OUTn
at the n-th output terminal of the circuit
101
.
Although not shown in FIG.
1
and described here, each of the third to (n-
1
)-th sections for the third to (n-
1
)-th channels has the same configuration and operation as the first, second, and n-th sections.
With the prior-art multichannel receiver circuit
101
shown in
FIG. 1
, the first to n-th sections for the first to n-th channels are formed and integrated on the semiconductor substrate
101
a
in the form of an IC. Thus, there is a disadvantage that a signal transmitted through one of the first to n-th channels is likely to be affected by another transmitted through an adjoining one or ones of these channels.
On the other hand, all of the first to n-th channels are not always used, in other words, there is a possibility that one or more channels is/are kept unused. Moreover, input of at least one of the first to n-th input signals may be stopped due to some fault such as transmission line disconnection. In these cases, the output signal of an unused channel or a channel having no input signal application is undefined (i.e., the channel in question is in the “don't care” state) and as a result, the said channel will enter its oscillation state that causes a noise with a large amplitude.
For example, as shown in
FIG. 2
, it is supposed that input of the first input signal S
IN1
for the first channel is suddenly stopped at the time to due to line disconnection while the second to n-th input signal S
IN2
to S
INn
for the rest of the channels are being inputted. In this case, the level of the first input signal is zero and thus, the first output signal S
OUT1
enters its oscillation state and generates a pulsed noise in the first channel. The noise thus generated in the first channel tends to affect the nearest second input signal S
IN2
by way of the substrate
101
a
or the IC package (not shown) at and after the disconnection time to. Thus, at and after the time to, there is a possibility that the second input signal S
IN2
includes a pulsed noise with a large amplitude. If so, the second output signal S
OUT2
includes a pulsed noise due to the noise of the second input signal S
IN2
, which degrades the signal to noise ratio (S/N) of the signal S
OUT2
in the second channel.
There is a possibility that some of the third to n-th output signals S
OUT3
to S
OUTn
include a pulsed noise due to the noise induced in the first channel.
Conventionally, since electric signals transmitted in parallel through multiple channels in the multichannel receiver circuit of this type have narrow bandwidths, the above-described disadvantage has occurred scarcely. In recent years, however, these receiver circuits have been highly integrated on a semiconductor substrate monolithically and at the same time, the signal speed for each channel has increased further. As a result, the above-described disadvantage of S/N degradation due to crosstalk has been becoming conspicuous.
With the prior-art multichannel receiver circuit
101
of
FIG. 1
, when one of the input signals S
IN1
to S
INn
of the first to n-th channels does not exist due to some cause, the said input signal enters its oscillation state and then, a pulsed noise with large amplitude is generated therein. The pulsed noise thus produced tends to affect the input side of the adjoining channel or channels (i.e., crosstalk occurs) by way of the substrate
101
a
or the IC package. Thus, a pulsed noise occurs in the input signal for the adjoining channel. This means that not only the input signal of the adjoining channel but also the noise thereof are amplified and outputted as the output signal S
OUT1
to S
OUTn
, resulting in S/N degradation due to crosstalk. This event becomes more conspicuous and serious as the signal speed increases.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a multichannel receiver circuit that suppresses effectively crosstalk or interference between the electric signals transmitted in parallel through multiple channels at high speed.
Another object of the present invention is to provide a multichannel receiver circuit that prevents the generation of oscillation state for each channel.
Still another object of the present invention is to provide a multichannel receiver circuit that improves the S/N for each channel.
The above objects together with others not specifically mentioned will become clear to those skilled in the art from the following description.
A

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