Multiplex communications – Wide area network – Packet switching
Patent
1992-10-01
1994-08-02
Bowler, Alyssa H.
Multiplex communications
Wide area network
Packet switching
395425, 395500, 395575, 370 859, 3642388, 3642402, 3642419, 3642444, 3642545, 3642601, 364DIG1, G06F 1300, G06F 1338
Patent
active
053353269
ABSTRACT:
The present invention is bus to bus interface for connecting a first bus to a second bus. A control means includes first and second control sequence means, substantially similar, for tracking and controlling the channels of data within a first and a second FIFO device. The first sequence control means includes first circular queue means for providing a predetermined number of slots, with each slot containing information regarding a channel of data already resident in first FIFO device, including the identity of the channel and the status of the channel, and containing information regarding a channel of data pending residence in first FIFO device, including the identity of the pending channel. The first sequence control means further includes first input pointer means for traversing first circular queue means, slot by slot, and if a slot contains the identity of a resident channel, then updating the status information in the slot of that resident channel, and if the slot does not contain the identity of a resident channel, then determining whether any channels are pending residence in first FIFO device, and if so inserting in the slot the identity of a pending channel and commencing transfer of the pending channel into first FIFO device, provided first FIFO device has room for the pending channel.
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Apostol George
Nguyen Uoc H.
Whang Lipson
Bowler Alyssa H.
Shah Alpesh M.
Xerox Corporation
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