Multichannel-capable bit error rate test system

Details Multichannel-capable bit error rate test system Multichannel-capable bit error rate test system

1999-11-02

2003-09-30

Chin, Wellington (Department: 2664)

Multiplex communications

Diagnostic testing

Loopback

C370S241000, C370S250000, C370S251000, C714S715000, C714S716000, C379S027010, C379S027030, C379S027040, C379S027050

Reexamination Certificate

active

06628621

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates in general to communication systems, and is particularly directed to a bit error rate test (BERT) system, that is programmably configurable to emulate one or more independent BERT generators and thereby produce a sequence of test frames. The test frames contain test pattern codes associated with respectively different time division multiplexed (TDM) digital communication channels that are not necessarily mutually contiguous within a plurality of TDM timeslots of a network communication frame serving digital communication circuits. The programmable BERT system of the invention is operative to selectively interface the sequence of test frames with digital communication units of a channel bank over a serial network interface and to measure thereover the performance of the digital communication units.
BACKGROUND OF THE INVENTION
The parameters of signals generated by digital communication equipments that interface with existing telecommunication networks are required to conform with prescribed industry (e.g., ANSI) standards. For example, a standard T
1
data frame (having a data transport rate of 1.544 Mbps) contains 193 bits, including a framing bit and 192 channel bits. The channel bits may be undivided (non-channelized), or may be ‘channelized’, by being subdivided into one or more timeslots or channels of some number of bits per channel, such as twenty-four basic rate (DS
0
) channels of eight bits each, as diagrammatically illustrated in FIG.
1
. As shown in
FIG. 2
, when employed for the transport of integrated services digital network (ISDN) channels, these twenty-four basic rate DS
0
channels (DS
0
-
0
, . . . , DS
0
-
23
) may be grouped in pairs of B
1
and B
2
bearer channels of eight bits each, and auxiliary (D and M) control channels associated with each pair of bearer channels.
A conventional (non-channelized) T
1
BERT device typically generates a single stream of 192 bits that are is inserted sequentially across the entire frame of data. As long as the T
1
circuit under test is non-channelized, such as a high data rate digital subscriber line (HDSL) or a fractional T
1
loop, this standard T
1
BERT device may be used, since all of the bits transmitted over the T
1
interface are delivered to only one circuit under test and therefore will be returned from that circuit in the order transmitted. However, if the T
1
circuit to be tested is channelized, such as one that is subdivided into channel units of a multi-unit channel bank, diagrammatically illustrated at
10
in
FIG. 3
, a conventional BERT device
12
cannot be used to test the circuit via the T
1
network interface
14
, since the channels of the channel units
16
of the channel bank
10
cannot be assumed to be ‘time sequence synchronous’.
More particularly,
FIG. 4
shows a series of T
1
test frames Frame
0
, Frame
1
, Frame
2
, . . . , each of which is comprised of a sequence of twenty-four test pattern codes Ax, Bx, . . . AAx (where x is the-frame number), as asserted onto the T
1
network interface
14
by the conventional non-channelized BERT device
12
. Each channel unit
16
in the channel bank
10
transmits its (single) associated byte in a respective test frame received from the BERT out its transmit port, which is then immediately looped back to its receive port, and returned over the T
1
network interface to the BERT device.
In an ideal world, each channel unit operates with zero latency, so that the bits of each successive test frame sourced from the BERT device will be received in exactly the same order as they are transmitted, enabling test frame pattern sync to be readily achieved in the BERT device's receiver. In the real world, however, the respective channel units of the channel bank
10
exhibit different degrees of latency. As a consequence, frames returned to the BERT device have bytes from some DS
0
s that are shifted in time, as shown diagrammatically in the non-limiting test frame sequence example of FIG.
5
. This means that the frames returned from the channel bank will not match the transmitted test frames, preventing the BERT device from achieving pattern sync.
To test a channelized T
1
network, therefore, a channelized BERT device, namely, one which is operative to test one channel at a time, must be employed. This individual testing of only one of the bank's (twenty-four) channel units is shown diagrammatically in
FIG. 6
, wherein each test frame of the test frame sequence Frame
0
, Frame
1
, Frame
2
, . . . contains only a single test code (B
0
, B
1
, B
2
, . . . ) associated with only a single selected channel (timeslot DS
0
-
1
). As further shown in
FIG. 7
, although the channel unit under test returns the transmitted test frames with a two frame latency, that delay poses no problem, since the bytes of the returned test pattern frames are received in exactly the same order as they are transmitted. However, a major shortcoming in testing channelized networks in this manner is the considerable time required to test all of the channels.
In addition to being unable to test a ‘channelized’ network, a conventional BERT device is also unable to test non-contiguous and non-adjacent channels, such as a frame of basic rate 3-DS
0
ISDN channels, shown diagrammatically in
FIG. 2
referenced above, or the frame of BR
1
/10 bits of a ten channel ISDN frame shown in
FIG. 8
, and described in U.S. Pat. No. 5,771,236, issued Jun. 23, 1998 to Sansom et al (hereinafter referred to as the '236 patent), entitled “Method for Increasing ISDN Channel Capacity of TDM Serial Communication Link for Digital Subscriber Line Channels,” assigned to the assignee of the present application and the disclosure of which is incorporated herein. The main problem in testing a non-adjacent channel configured ISDN frame is the fact that the (D/M) data within the auxiliary control channels is no longer contiguous with that in the adjacent bearer channels, due to the presence of interleaved bits. A conventional BERT device cannot ‘skip’bits. Similarly, the D channels of a BR
1
/10 ISDN frame occupy multiple DS
0
channels that are non-contiguous with their associated bearer channels. Since the data within a channel is no longer contiguous, and is not transferred across adjacent DS
0
s, a conventional BERT device cannot be used to test across the network interface. Instead, as diagrammatically illustrated in
FIG. 9
, a separate single channel BERT device is required to test each channel, increasing the number and cost of system resources.
SUMMARY OF THE INVENTION
In accordance with the present invention, the shortcomings of conventional BERT schemes, such as those described above, are effectively obviated by a new and improved bit error rate test system that is programmably configurable to emulate one or more independent BERT generators that generate channel pattern test codes for testing one or more channels of a telecommunication channel bank. In effect, the channel pattern test codes generated by the programmably configurable BERT generator of the present invention may be considered to be ‘pseudo’subscriber channels—conveying test pattern codes, as the effective functionality of the output codes generated by the BERT generator is to test the channels, rather than deliver information signals via the channels to circuits served by associated channel units.
For this purpose, a data channel-specific BERT generator unit is programmed to implement one or more individual BERT pattern generators, depending upon the type or format of channelization of the circuits under test. Each BERT pattern generator generates a respective test code pattern that is used to form successive test frames for testing one or more data channels. The BERT test patterns are coupled to a data channel-specific network test frame buffer, which is programmably configurable under software control to provide plural channel registers that store an entire test frame for transmission to the channel circuits or units under test.
The input/output addressing sche

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