Multiplex communications – Wide area network – Packet switching
Patent
1996-02-14
1997-04-15
Blum, Russell W.
Multiplex communications
Wide area network
Packet switching
3701051, 3701052, 3701054, 370 201, 379 10, H04J 314
Patent
active
056217200
ABSTRACT:
A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and subrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. A second embodiment of the invention partitions the system into a base subsystem, a communications link and a remote subsystem, collectively referred to as a distributed architecture system. The distributed architecture system provides all of the performance monitoring and testing capabilities of the existing access system. The distributed architecture system provides a mechanism to transport a plurality of asynchronous and rate independent signals across the link to permit remote testing of digital and voice DS0 frequency circuits. In the preferred embodiment, the link that connects the base to the remote system is a standard DS1 channel. The clocks for the transmit and receive paths are derived from the same source, thus providing a common reference clock to both ends of the link. At the remote site, the channels undergoing test are embedded DS0 channels within a DS3 signal accessed through a DS3 interface at the base site.
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Bronte Jeffery S.
Hartmann Paul R.
Lever Mark J.
Pope Kevin T.
Applied Digital Access, Inc.
Blum Russell W.
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