Multibus sequential processor to perform in parallel a plurality

Details Multibus sequential processor to perform in parallel a plurality Multibus sequential processor to perform in parallel a plurality

1991-01-29

1994-04-05

Lall, Parshotam S.

Boots, shoes, and leggings

364DIG1, 3642294, 3642541, 3642542, 3642543, G06F 1300

Patent

active

053013441

ABSTRACT:
A reconfigurable sequential processor includes a data bank for storing data to be processed; a programmable logic block address generator for addressing data in the data bank; a programmable logic block arithmetic unit responsive to the data bank for processing the data addressed by the programmable logic block address generator; an address generator hardware configuration file having a plurality of configuration files for configuring the programmable logic block address generator in one of a plurality of addressing configurations in response to an address operational code; an arithmetic hardware configuration file having a plurality of configuration files for configuring the programmable logic block arithmetic unit in one of a plurality of processing configurations in response to an arithmetic operational code; and for delivering a series of operational codes to each configuration file for enabling the programmable logic block address generator and the programmable logic block arithmetic unit to be configured to perform sequentially a corresponding series of arithmetic logic operations on the data in the data bank.

REFERENCES:
patent: 4590557 (1986-05-01), Lillie
patent: 4604690 (1986-08-01), Crabtree et al.
patent: 4747070 (1988-05-01), Triottier et al.
patent: 4761755 (1988-08-01), Ardini, Jr. et al.
patent: 5014193 (1991-05-01), Garner et al.
patent: 5109503 (1992-04-01), Cruickshank et al.
patent: 5125081 (1992-06-01), Chiba
patent: 5142469 (1992-08-01), Weisenborn

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