Multibit recyclic pipelined ADC architecture

Details Multibit recyclic pipelined ADC architecture Multibit recyclic pipelined ADC architecture

2011-05-24

2011-05-24

Nguyen, Linh V (Department: 2819)

Coded data generation or conversion

Sample and hold

C341S118000, C341S120000, C341S155000, C341S161000, C341S172000

Reexamination Certificate

active

07948410

ABSTRACT:
An apparatus is provided. The apparatus comprises a sample switch, a sampling capacitor, an amplifier, feedback branches, a second hold switch, an N-bit converter pair, a third hold switch, and an M-bit converter pair. The sample receives an input signal and is actuated by a sample signal. The sampling capacitor is coupled to the sample switch. The amplifier has a first input terminal that is coupled to the sampling capacitor. The feedback branches are coupled between the output terminal of the amplifier and the first input terminal of the amplifier, with each feedback branch including a feedback capacitor, and a first hold switch that is coupled to the feedback capacitor. The second hold switch is coupled to the sampling switch. The N-bit converter pair is coupled to the sampling switch and to the second hold switch. The third hold switch is coupled to at least one of the feedback branches, and the M-bit converter pair is coupled to the output terminal of the amplifier and to the third hold switch.

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