Multiaccumulator sigma-delta fractional-N synthesis

Details Multiaccumulator sigma-delta fractional-N synthesis Multiaccumulator sigma-delta fractional-N synthesis

1990-04-30

1991-10-08

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

331 25, 332127, 455 76, 455119, H03L 718

Patent

active

050558021

ABSTRACT:
A fractional-N synthesizer employing at least a second order sigma-delta modulator is disclosed. The most significant bits from the output accumulator of the sigma-delta modulator are used as the carry out control for the variable divisor of the loop divider. Modulation to the synthesizer is introduced as part of the digital number input to the sigma-delta modulator and spurious signal output is reduced by selection of a large number as the denominator of the fractional portion of the loop divider divisor.

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J. Candy, "A Use of Double Integration in Sigma Delta Modulation", IEEE Transactions on Communications, vol. Com 33 No. 3, Mar. 1985 pp. 249-258.

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