Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1998-12-02
2001-03-13
Gaffin, Jeffrey (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S255000, C430S313000, C029S852000
Reexamination Certificate
active
06201194
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to the production of chip carriers or printed circuit boards having multiple voltage planes, and more particularly to chip carriers, especially organic chip carriers, having multiple voltage planes separated by a dielectric material with plated through holes extending from one surface to the other through both of the voltage planes and through the dielectric material separating the voltage planes.
BACKGROUND INFORMATION
In the past, one typical technique for forming chip carriers having multiple voltage planes, i.e., at least two voltage planes, and multiple signal planes, i.e., at least two signal planes (2
s/
2
p
) using organic dielectric material has relied on mechanically drilling holes in the voltage planes and particularly mechanically drilling holes in the voltage planes after they have been laminated to a substrate such as FR4 material, which is a glass reinforced epoxy resin. This drilling has several drawbacks. First, drilling is extremely costly in that individual holes must be drilled successively and precisely on a grid. Second, the minimum hole diameter is limited, typically the minimum being from 0.006 inches to 0.008 inches, which results in a minimum land diameter of 0.010 to 0.014 inches, particularly in subtractive processing. Moreover, drilling can lead to reliability problems caused by cathodic and anodic filament plating growth along the glass fibers, which may be damaged by the drilling, and this causes either failure or out of specification parts. Additionally, power distribution in a typically drilled organic chip carrier is poor due to the large amount of copper that must be etched away to provide clearance or tolerance for the plated through holes due to the relatively large grid size required.
All of these factors result in a minimum I/O grid of 0.018 inches to 0.02 inches. As the technology advances, a desirable I/O grid is of 0.010 inches to accommodate flip chip attachment (i.e., solder ball or C4 joints).
SUMMARY OF THE INVENTION
According to the present invention, a technique for forming a chip carrier, and preferably an organic chip carrier, having two voltage planes and at least two signal planes is provided. The technique includes bonding a first layer of photolithographic dielectric material to a first metal layer and exposing the first layer of dielectric material to a pattern of radiation to provide at least one opening through the first layer of the dielectric material to be developed in subsequent processing.
A second metal layer is bonded to the first layer of photoimageable material on the opposite side from the first metal layer. Holes are etched in the first and second metal layers which correspond to and are larger than each of the patterns on said openings in the first layer of dielectric material. The exposed pattern on the first layer of dielectric material is then developed to form at least one opening corresponding to the exposed pattern through the first and second metal layers and through the first layer of dielectric material, with the openings in the first and second metal layers being larger than the developed opening in the first dielectric material.
Second and third layers of photoimageable dielectric material are applied on the first and second metal layers, respectively. The second and third layers of photopatternable dielectric material are photopatterned and developed to provide openings in each of the second and third layers of dielectric material corresponding to each of the holes in the first layer of dielectric material and the holes in the first and second metal layers. The exposed surfaces of at least the second dielectric material, and preferably both the second and third dielectric material, are circuitized and the holes plated such that there is circuitry on at least one side, and preferably both sides, and one plated through hole that extends all the way through the dielectric material. The circuitization may be carried out with an additive process sequence, a full subtractive process sequence, or a semiadditive pattern plate process sequence. Preferably, the layers of metal and the circuitry are formed of copper, and preferably the etching of the holes in the layers of copper is performed utilizing photolithographic techniques. The circuitization also preferably is by photolithographic process.
REFERENCES:
patent: 4150421 (1979-04-01), Nishihara et al.
patent: 4211603 (1980-07-01), Reed
patent: 4729061 (1988-03-01), Brown
patent: 4795693 (1989-01-01), Ors et al.
patent: 4830704 (1989-05-01), Voss et al.
patent: 4849284 (1989-07-01), Arthur et al.
patent: 5021821 (1991-06-01), Suzuki
patent: 5026624 (1991-06-01), Day et al.
patent: 5146674 (1992-09-01), Frankeny et al.
patent: 5262280 (1993-11-01), Knudsen et al.
patent: 5263243 (1993-11-01), Taneda et al.
patent: 5298117 (1994-03-01), Hanson et al.
patent: 5300402 (1994-04-01), Card, Jr. et al.
patent: 5334487 (1994-08-01), Kindl et al.
patent: 5366846 (1994-11-01), Knudsen et al.
patent: 5387493 (1995-02-01), Imabayashi et al.
patent: 5451721 (1995-09-01), Tsukada et al.
patent: 5473120 (1995-12-01), Ho et al.
patent: 5883335 (1999-03-01), Mizumoto et al.
patent: 6027858 (2000-02-01), Jones et al.
patent: 3-138653 (1991-06-01), None
patent: 08-018234 (1996-01-01), None
Lauffer John M.
Magnuson Roy H.
Markovich Voya R.
Welsh John A.
Cuneo Kamand
Gaffin Jeffrey
Hogg William N.
International Business Machines - Corporation
LandOfFree
Multi-voltage plane, multi-signal plane circuit card with... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multi-voltage plane, multi-signal plane circuit card with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-voltage plane, multi-signal plane circuit card with... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2549037