Multi-virtual DMA channels, multi-bandwidth groups, host based c

Details Multi-virtual DMA channels, multi-bandwidth groups, host based c Multi-virtual DMA channels, multi-bandwidth groups, host based c

1992-12-22

2000-02-15

Follansbee, John A.

Electrical computers and digital processing systems: multicomput

Computer-to-computer protocol implementing

G06F 1300

Patent

active

060264438

ABSTRACT:
A control memory is provided for storing the control and state information of a number of virtual direct memory access (DMA) channels. A control memory arbiter and a control memory data bus are also provided to arbitrate accesses to the control memory to facilitate asynchronous transmit and receive. Separate areas in the control memory are provided for storing the control and state information of the transmit DMAs, and the receive DMAs. Additionally, descriptive information about the transmit/receive data ring and its descriptor, the data packet being transferred and its cells are also stored for the transmit and receive DMAs. The control memory is also used to stored a programmable bandwidth group (BWG) table comprising a plurality of BWG index entries for bandwidth selection. A Segmentation And Reassembly (SAR) module which cellifies transmit packets and reassembly receive packets on the host computer is also provided for segmenting transmit packets into transmit cells for transmission, and reassembling receive cells into receive packets. Two series of FIFOs are provided for staging the transmit and receive cell payloads. Lastly, complement to the SAR module, a media cell manager (MCM) module is provided for packing the transmit cell payloads before their transmission, and unpacking the receive cell payloads upon their receipt. The cyclic redundancy check (CRC) value for each transmit packet is calculated incrementally. Transmit tags are used to differentiate the transmit cell payloads from the packet header and packing instructions; and receive tags are used to differentiate the receive cell payloads from the packet header and the end of packet marker.

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