Multi-valued signal decoding circuit having bit synchronization

Details Multi-valued signal decoding circuit having bit synchronization Multi-valued signal decoding circuit having bit synchronization

1994-11-08

1997-07-01

Chin, Wellington

Pulse or digital communications

Multilevel

375360, H04L 2534

Patent

active

056446004

ABSTRACT:
A multi-valued signal decoding circuit is disclosed which has a circuit for detecting a bit synchronization signal included in the multi-valued data signal transmitted in the form of a packet signal, a circuit for detecting by this detected output a timing of a transition of the bit synchronization signal, a circuit for sampling and holding the bit synchronization signal by using sampling pulses generated on the bases of said timing, and a circuit for decoding the multi-valued data signal by using decoding reference voltages formed on the basis of the sampled and held level.

REFERENCES:
patent: 4696016 (1987-09-01), Rozema et al.
patent: 4852124 (1989-07-01), Raucci
patent: 5140620 (1992-08-01), Woodward
patent: 5267267 (1993-11-01), Kazawa et al.
patent: 5539784 (1996-07-01), Brauns et al.

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