Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Utilizing three or more electrode solid-state device
Patent
1995-10-13
1998-02-17
Callahan, Timothy P.
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Utilizing three or more electrode solid-state device
327429, 36518501, 36518503, 36518514, H03K 17687
Patent
active
057195200
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a semiconductor device, and in particular to a high-performance MOS circuit.
BACKGROUND ART
Source-follower circuits are frequently used to drive impedance loads, especially in applications employing analog or multiple-valued signals. Such a circuit is depicted in FIG. 1. This diagram indicates a source-follower circuit comprised of one NMOS transistor (abbreviated as "NMOS") (M10) and a load capacitance (C10); when V.sub.IN (101) is greater than V.sub.T (the threshold voltage of M10), current flows to increase V.sub.OUT (102) until
If the gate electrode of an NMOS in a source-follower configuration is made floating, and several input gates are capacitively coupled to the floating gate, as shown in FIG. 2, then the potential of the floating gate (.phi.F) (201) becomes a linearly weighted summation of the voltages applied to the inputs: ##EQU1## where n is the number of input gates, C.sub.1 to C.sub.n are the coupling capacitances to the floating gate, and C.sub.total is the sum of all coupling capacitances. Therefore, by adjusting the coupling capacitance ratios and the input voltages, the floating gate potential can assume any desired voltage. In this circuit, V.sub.OUT (202) will rise until it equals .phi.F-V.sub.T.
One application of this circuit is the simple 2-bit digital-to-analog (D/A) converter depicted in FIG. 3. By setting the coupling ratio C.sub.1 :C.sub.2 =1:2, and applying 0 V or 5 V to the input gates V.sub.1 (301) and V.sub.2 (302), four possible states are obtained on the floating gate (303), as shown in Table 1 shown in FIG. 13. In Table 1, the symbol "WL" designates a high level signal applied to the respective inputs, in this case, the high level signal is 5 V. In this manner, the digital signals at V.sub.1 and V.sub.2 are converted into analog signals at V.sub.OUT (304).
DISCLOSURE OF THE INVENTION
The present invention discloses a semiconductor circuit comprising at least a single n-channel or p-channel MOS transistor in a source-follower configuration. The input of this source-follower circuit is a floating gate which is capacitively coupled to multiple control gates. The voltages applied to the control gates and the coupling ratios of the control gates determine the potential of the floating gate. When a voltage supply is applied to the drain electrode of the source-follower circuit, the source-electrode potential will nearly equal the floating gate potential, provided that V.sub.T .apprxeq.0 in Equation 1.
The above semiconductor device realizes a single-transistor, read-only memory cell capable of non-volatile storage of multiple-valued or analog data. The data is programmed into the cell by a single masking step during the fabrication process. This cell can be replicated into a matrix of several rows and columns, with all cells in one row sharing a common word line and all cells in one column sharing a common bit line, thus achieving a high-density memory-cell array. Furthermore, this cell does not consume any standby-by power.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit diagram showing a typical NMOS source-follower circuit.
FIG. 2 is a circuit diagram showing an NMOS source-follower circuit with multiple input gates capacitively coupled to its floating gate electrode.
FIG. 3 is a circuit diagram showing a 2-bit digital-to-analog converter using a floating-gate NMOS source follower.
FIG. 4 is a circuit diagram showing the circuit of Embodiment 1, for the case of storing the data value "2".
FIG. 5 is a circuit diagram showing the circuit of Embodiment 2, for the case of storing the data value "2".
FIG. 6 is a circuit diagram showing the circuit of Embodiment 3, for the case of storing the data value "2".
FIG. 7 is a circuit diagram showing a sample array of cells described by Embodiment 3.
FIG. 8 shows measured operation data of the circuit of Embodiment 3.
FIG. 9 is a photomicrograph of 4-valued and 8-valued fabricated test cells.
FIG. 10 is a schematic diagram of the top-view and cross-section of the invention
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Shibata & Ohmi "1991 Symposium On VLSI Technology; Digest Of Technical Papers; Jun. 2-4 1992", Seattle, XP342723.
IEEE Transactions On Electron Devices, vol. 39, No. 6, Jun. 1992, New York, pp. 1444-1455, XP271791 Shibata & Ohmi "A Functional MOS Transistor Featuring Gate-Level Weighted Sum And Threshold Operations."
Au Rita Wai-Chi
Ohmi Tadahiro
Shibata Tadashi
Callahan Timothy P.
Shibata Tadashi
Zweizig Jeffrey
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