Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
1998-08-03
2001-02-27
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
C438S907000, C438S908000
Reexamination Certificate
active
06194232
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a wafer processing method that offers concurrent processing of a plural number of wafer lots in different wafer tanks for reducing the total processing time and increasing through-put.
2. Description of the Prior Art
Conventional methods for processing semi-conductor wafers use sequencing by lots. In other words, one lot of wafers has to complete a processing step in one tank before another lot of wafers may be processed in another tank.
FIG. 1
shows such an example. There are three lots
1
,
2
and
3
of wafers that are stored and assigned respectively at three different stages
10
,
20
and
30
. There are four different tanks
11
,
12
13
and
14
. Each tank may perform a different wafer process such as depositing photo resist, etching processing, etc. There is a passage
15
for communicating the stages with each tank. For instance, lot
1
may be assigned a process sequence number
21
and be processed in the tank
11
, lot
2
be assigned a sequence number
22
for processing in the tank
12
, and lot
3
be assigned a sequence number
23
to be processed in the tank
13
.
The problem with the conventional methods is that all the lots to be processed must be sequenced one after another. For example, lot
2
cannot be transported to the tank
12
until after the lot
1
at the tank
11
has completed its processing thereof. Lot
3
cannot be moved to the tank
13
until after lot
1
and lot
2
have completed processing in tanks
11
and
12
. Therefore, the queue time is long and adversely affects total through-put.
FIG. 2
further explains the process flow of a conventional sequenced wafer lot processing method. Step
411
is to load different lots of wafers to different stages. Step
412
selects a required processing recipe (such as depositing photoresistance or etching the wafer) for each lot and starting execution of the processing. Step
413
is to set the processing priority for each lot, including assigning the starting sequence number, position number and tank number, etc. Step
414
involves scanning the wafer in a wafer lot to read the lot information. Step
415
involves loading the lot information into a computer memory buffer. In step
416
, the wafer from a fixed lot to be processed is loaded into a specific tank. Step
417
performs one wafer processing such as depositing photoresistance on the wafer. Step
418
involves moving the wafer to its original location (original lot). At step
419
, there are two possible routes. If this is not the last wafer in the lot, then processing returns to the step
415
for processing the next wafer.
If it is the last wafer in the lot, then step
420
further checks if it is the last lot. If the answer is negative, processing returns again to step
415
for another cycle of processing through the step
421
. If the answer is positive, then processing ends at step
422
.
The conventional processing method set forth above is basically a sequential operation. Each lot will be assigned a sequence number (step
413
). Once assigned, it will be waiting in a queue until a preceding lot has completed processing even if it takes a different processing step at a different tank.
SUMMARY OF THE INVENTION
In view of aforesaid disadvantages, it is therefore an object of this invention to provide a wafer processing method that can perform multiple processings for a plurality of wafer lots concurrently at different tanks. Total processing time is thus greatly shortened while processing facilities can be more efficiently used, and total productivity can therefore be greatly increased.
The method according to this invention generates a FINISH signal at the end of wafer processing in a tank. Once the FINISH signal is detected and the tank number is known, the sequence information of the next wafer lot which will use that tank is loaded into the memory so that the next wafer lot may be transported to that tank once the finished lot has been moved out of that tank. The processing of the wafer lots thus may be dynamically assigned and independently performed, so that a plurality of wafer lots may be processed at different tanks concurrently. Total processing time thus may be greatly reduced.
The method of this invention may be used with various processing steps such as depositing photoresistance, wafer etching and others. Each wafer lot will be assigned with a starting sequence number, position number, tank number and wafer serial number.
REFERENCES:
patent: 5024570 (1991-06-01), Kiriseko et al.
patent: 5402350 (1995-03-01), Kline
patent: 5855681 (1999-01-01), Maydan et al.
patent: 5928389 (1999-07-01), Jevtic
Booth Richard
Liauh W. Wayne
Lindsay Jr. Walter L.
ProMos Technology, Inc
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