Multi-threaded microprocessor architecture utilizing static inte

Details Multi-threaded microprocessor architecture utilizing static inte Multi-threaded microprocessor architecture utilizing static inte

1992-02-25

1995-04-04

Eng, David Y.

Boots, shoes, and leggings

3642318, 36494834, G06F 924, G06F 930, G06F 938

Patent

active

054044693

ABSTRACT:
A static interleaving technique solves the problem of resource contention in a very long instruction word multi-threaded microprocessor architecture. In the static interleaving technique, each function unit in the processor is allocated for the execution of an instruction from a particular thread in a fixed predetermined time slot in a repeating pattern of predetermined time slots. The fixed predetermined pattern of time slots represents the resource constraints imposed on the hardware to resolve the contention for computing resources among the instruction threads. The strategy of resource allocation is exposed to a parallel compiler which organizes a sequence of instructions into the horizontal instruction words which form each thread so as to maintain the data dependencies among the instructions and to take into account the fixed predetermined allocation of hardware resources.

REFERENCES:
patent: 5226125 (1993-07-01), Balmer
"Distributed Instruction Set Computer Architecture", IEEE Trans. on Computer, 1991, L. Wang and C. L. Wu.
"A Benchmark Evaluation of a Multi-threaded RISC Porcessor Architecture", Proc, of the International Conference on Parallel Processing, 1991, R. G. Prasadh and C. L. Wu.
"Computer Architecture and Parallel Processing" by Kai Hwang & Faye A. Briggs, 1984, McGraw-Hill, Inc, pp. 20-40.

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