Multi-thread parallel processing sigma-delta ADC

Details Multi-thread parallel processing sigma-delta ADC Multi-thread parallel processing sigma-delta ADC

2005-08-16

2005-08-16

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

C341S155000

Reexamination Certificate

active

06930625

ABSTRACT:
An analog input signal is digitized by first sampling the analog signal to produce a first sequence of analog samples representing successive magnitudes and de-interleaving the first sequence into a set of two or more second sequences. A parallel processing, sigma-delta modulator then processes the set of second sequences to produce a set of two or more third sequences of digital data elements which are then interleaved to produce a fourth sequence of digital data elements. The fourth sequence is then digitally filtered and decimated to produce a fifth sequence of digital data elements representing successive magnitudes of the analog input signal.

REFERENCES:
patent: 5345236 (1994-09-01), Sramek, Jr.
patent: 6075820 (2000-06-01), Comino et al.
patent: 6111531 (2000-08-01), Farag
patent: 6518905 (2003-02-01), Siferd

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