Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
2006-04-06
2009-12-08
Phunkulh, Bob A (Department: 2477)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S428000, C710S052000
Reexamination Certificate
active
07630389
ABSTRACT:
Systems and methods for generating synthesizable code representing first-in first-out (FIFO) memories may be used to produce FIFO memories for multi-threaded processing. A single FIFO memory is shared between the threads to conserve die area, however each thread may be executed independently, as if each thread has a dedicated FIFO memory. A synthesizable code generator produces synthesizable code for a sender interface, storage, receiver interface, and other features that are specified by a programmer. The other features may reduce power consumption or improve timing. The code generator is used to efficiently produce different variations of FIFO memories.
REFERENCES:
patent: 2005/0114612 (2005-05-01), Bombal
Alfieri Robert A.
Oliveira Marcio T.
NVIDIA Corporation
Patterson & Sheridan LLP
Phunkulh Bob A
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