Multi-thread execution method and parallel processor system

Data processing: software development – installation – and managem – Software program development tool – Translation of code

Reexamination Certificate

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C717S161000

Reexamination Certificate

active

07082601

ABSTRACT:
In a parallel processor system for executing a plurality of threads in parallel to each other by a plurality of thread execution units, the respective thread execution units allow for forking of a slave thread from an individual thread execution unit into another arbitrary thread execution unit. The respective thread execution units are managed in three states, a free state where fork is possible, a busy state where a thread is being executed, and a term state where a thread being terminated and yet to be settled exists. At the time of forking of a new thread, when there exists no thread execution unit at the free state, a thread that the thread execution unit at the term state has is merged into its immediately succeeding slave thread to bring the thread execution unit in question to the free state and conduct forking of a new thread.

REFERENCES:
patent: 5546593 (1996-08-01), Kimura et al.
patent: 5890008 (1999-03-01), Panwar et al.
patent: 5913059 (1999-06-01), Torii
patent: 5970250 (1999-10-01), England et al.
patent: 6003066 (1999-12-01), Ryan et al.
patent: 6035374 (2000-03-01), Panwar et al.
patent: 6389446 (2002-05-01), Torii
patent: 6694425 (2004-02-01), Eickemeyer
patent: 6697935 (2004-02-01), Borkenhagen et al.
patent: 0 330 836 (1989-09-01), None
patent: 10-27108 (1998-01-01), None
patent: 10-78880 (1998-03-01), None
patent: WO 1998/043192 (1998-10-01), None
S. Torii et al. “Control Parallel On-Chip Multi-processor: MUSCAT,” Proceedings of the Parallel Processing Symposium JSPP97 (May 1997), pp. 229-236, Japanese Society of Information Processing Engineers of Japan.
R. Kobayashi et al., “SKY: A Processor Architecture that Exploits Instruction-level Parallelism in Non-numerical Applications,” Proceedings of the Parallel Processing Symposium JSPP98 (Jun. 1998), pp. 87-94, Japanese Society of Information Processing Engineers of Japan.
G. S. Sohi et al., “Multiscalar Processors,” 22ndInternational Symposium on Computer Architecture (Jun. 1995) pp. 414-425, IEEE Computer Society Press, Santa Margherita Ligure, Italy.
S. Gopal et al., “Speculative Versioning Cache,” Proceedings of the 4thInternational Symposium on High Performance Computer Architecture (Feb. 1998) IEEE Computer Society Technical Committee, Las Vegas, Nevada.

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