Computer graphics processing and selective visual display system – Computer graphics processing – Graph generating
Reexamination Certificate
1998-12-14
2001-06-19
Luu, Matthew (Department: 2672)
Computer graphics processing and selective visual display system
Computer graphics processing
Graph generating
C345S111000, C345S502000, C345S505000, C709S241000
Reexamination Certificate
active
06249288
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention generally relates to computer display systems; and in particular, the present invention relates to a display controller supporting multiple overlays on a computer display.
2. Background of the Invention
A graphics display system of a personal computer must support a complex video display including multiple windows of text, graphical data and movie images.
FIG. 1
is a block diagram of a typical graphics display system
100
. System
100
includes display controller
101
, system processor
102
and memory interface
103
, all communicating over a system bus
106
. System
100
further includes frame buffer memory
104
which is depicted here as including frame buffers
104
a
,
104
b
, and
104
c
and coupled to system bus
106
through memory interface
103
. Frame buffer memory
104
typically has the capacity to store pixel data for at least one frame of a video display image. Video images are generally represented as sequences of frames where each frame is a matrix of pixels that vary in color and intensity according to the image displayed.
Display controller
101
and system processor
102
access frame buffer memory
104
via system bus
106
. System processor
102
stores video data, or pixel data, for each frame of video image in frame buffer memory
104
. Display controller
101
retrieves the stored video data and processes the data to generate graphics commands and data for driving a computer display
105
. Graphics display system
100
is intended to be representative of those used in conventional general purpose personal computers and elements of system
100
are illustrative of those found in most personal computers.
Computer display
105
is a raster display monitor and display video images based on graphics commands and data generated by display controller
101
. Display
105
can be any cathode ray tube (CRT) monitor or raster display monitor. Display
105
can also be any liquid crystal display (LCD) monitor. Display
105
displays a screen of image by scanning each line of pixel data horizontally, starting from the upper-left corner. After completing scanning a field of image (i.e. a full screen), the scan beams return to the upper-left corner to begin scanning and displaying the next field of pixel data. In general, the fields of pixel data are scanned on display
105
at a standardized display rate in the range of 60 to 85 frames/sec. Display controller
101
generates sync signals to align the display data with the scan beams. Typically, display controller
101
issues a vertical sync signal at the beginning of each display field (i.e. the upper-left corner of display
105
) and a horizontal sync signal at the beginning of each scan line.
To compose a field of pixel data, display controller
101
accesses pixel data stored in frame buffers
104
a-c
for processing. When a video image includes multiple overlays, display controller
101
initiates a single control thread to process the pixel data for the video image. The control thread generates graphics commands and data, hereinafter cumulatively called display signals, for all the overlays within the frame of video image. Because only one control thread is used to process pixel data for all of the overlays, display controller
101
processes pixel data for each overlay in a lock-step fashion. Display controller
101
has poor memory latency tolerance because the processing of pixel data is limited by the slowest process required for a particular overlay. The latency in processing can cause the display image to suffer the effect of tearing or rolling.
It would be desirable to provide a display controller capable of processing pixel data at an improved rate so that the computer display can transition seamlessly between each frame of display images, thereby eliminating image tearing or rolling.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a primitive for execution on a display controller in a graphics display system which improves latency tolerance and ensures seamless transitions between each frame of display images. The primitive of the present invention is executed on a display controller including a display processor, a bank of FIFO memories, an optional graphics processing unit, and a digital-to-analog converter (DAC). The primitive enables the display processor to process a number of control threads independently of each other, thus improving the performance of the display processor when generating display signals for a display field. The primitive of the present invention is advantageously applied to a graphics display system to ensure seamless transitions of screen images.
The display processor executes the primitive of the present invention for displaying video images on a computer display where the video images include multiple overlays. The primitive includes the steps of (1) activating a starting thread, (2) activating multiple control threads to execute a first program, where the first program involves processing pixel data for a first frame of video image and each of the control threads generates display signals for each of the overlays in the first frame of video image, (3) processing the multiple control threads, (4) determining whether processing of a first one of the threads is a last thread to be processed, and (5) if processing of the first one of the threads is a last thread to be processed, reactivating the multiple control threads to process pixel data for a second frame of video image.
The above described method can also include the step of inactivating the first one of the threads if the first one of the threads is not the last thread to be processed.
In another embodiment, the step of reactivating the multiple control threads to process pixel data for a second frame of video image in the above described method can include the step of reactivating the threads to execute the first program when the second frame of video image is the same as the first frame of video image. Furthermore, the reactivating step can also include the step of reactivating the threads to execute a second program when the second frame of video image is different from the first frame of video image.
In yet another embodiment, the above described method can also include the steps of synchronizing the display signals and transmitting the display signals to the computer display.
The present invention is better understood upon consideration of the detailed description below and the accompanying drawings.
REFERENCES:
patent: 5313574 (1994-05-01), Beethe
patent: 5313575 (1994-05-01), Beethe
patent: 5345588 (1994-09-01), Greenwood
patent: 5561811 (1996-10-01), Bier
patent: 5828848 (1998-10-01), MacCormack
patent: 5953530 (1999-09-01), Rishi
patent: 5964843 (1999-10-01), Eisler
patent: 6005575 (1999-12-01), Colleran
patent: 6049390 (2000-04-01), Notredame
ATI International SRL
Cook Carmen C.
Kwok Edward C.
Luu Matthew
Sajous Wesner
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