Multi-tap digital delay line

Details Multi-tap digital delay line Multi-tap digital delay line

1993-01-15

1994-12-20

Sikes, William L.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327261, 327 72, H03K 5153

Patent

active

053748603

ABSTRACT:
A programmable digital delay line having N delay elements, two multiplexers connected to the output of the delay elements, and a comparator connected to the outputs of the multiplexers is disclosed. The invention teaches an apparatus and a method of delaying a signal, while reducing the number of delay elements and the number of connections to multiplexers. In a first embodiment of the invention, the delay elements are inverters or differential delay elements. In a second embodiment, the delay elements are differential delay elements.

REFERENCES:
patent: 3668532 (1972-06-01), Potash
patent: 5049766 (1991-09-01), van Driest et al.
patent: 5063311 (1991-11-01), Swapp
patent: 5097489 (1992-03-01), Tucci
W. D. Llewellyn et al., "A 33 Mb/s Data Synchronizing Phase-Locked Loop Circuit," Feb. 1988, IEEE ISSCC Digest of Technical Papers, vol. 31, pp. 12-13.
National Semiconductor Mass Storage Handbook, 1989, pp. 2-38 and 2-39.
B. Kim, "High Speed Clock Recovery in VLSI Using Hybrid Analog/Digital Techniques," Memorandum No. UCB/ERL M90/50, Jun. 6, 1990, Elec. Research Lab., UC Cal., Berkeley, CA, p. 81.

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