Multi-system bus connected via interface side buffering intersta

Details Multi-system bus connected via interface side buffering intersta Multi-system bus connected via interface side buffering intersta

1989-05-30

1992-06-09

Lee, Thomas C.

Boots, shoes, and leggings

364DIG2, G06F 1336, G06F 1340

Patent

active

051214857

ABSTRACT:
A microprocessor system includes interstage buffer circuits and a slave system. The interstage buffer circuits include data signal buffer circuits (8a, 8b) and a swap buffer circuit (9), connected in parallel with the data signal buffer circuits (8a, 8b), for performing bit width conversion. The slave system is connected to a bus for connecting an interstage control signal buffer circuit and an interface control signal buffer circuits, a bus for connecting an interstage address signal buffer circuit and an interface address signal buffer circuit, and a bus for connecting the buffer circuits (8a, 9, 8b) and an interface data signal buffer circuit.

REFERENCES:
patent: 4511969 (1985-04-01), Koenig et al.
patent: 4833599 (1989-05-01), Colwell et al.
patent: 4837677 (1989-06-01), Burrus, Jr. et al.
patent: 4896256 (1990-01-01), Roberts
patent: 4901224 (1990-02-01), Ewert
patent: 4912636 (1990-03-01), Margar et al.
Intel Multibus Specification 1983, pages 2-1-2-18; 4-1-4-28; and 5-1-5-22.

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