Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-12-22
2001-06-19
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185200, C365S185330
Reexamination Certificate
active
06249455
ABSTRACT:
SUMMARY OF THE INVENTION
1. Field of the Invention
The present invention relates to a multi-step pulse generating circuit for a flash memory, and more particularly to a multi-step pulse generating circuit for a flash memory to reduce chip area and to prevent coupling by generating multi-step pulse with simple devices, not using complicated devices.
2. Description of the Prior Art
Multi-step pulse is used to improve threshold voltage level of a flash memory cell when the cell is erased or programmed. In this case, there is a problem in that the threshold voltage level of the cell may be improved, but device area thereof increases.
FIG. 1
is a circuit diagram to describe a conventional multi-step pulse generating circuit for a flash memory.
According to an enable signal EN, a first comparator COM
11
receives the reference voltage VREF and the output fb of the first comparator COM
11
, and outputs after comparing them. Then, to operate the first comparator COM
11
, VREF and fb, that is the input voltage of the first comparator COM
11
, should have the same fixed potential. The output of the first comparator COM
11
is entered to a second comparator COM
12
after being dropped as much as uniform potential via the first through third resistors R
1
to R
3
.
On the other hand, the input voltage VPPI generated from a positive charge pump circuit
10
is dropped to uniform potential according to the resistance of a diode chain
13
driven by a switch circuit
12
operating depending on a high voltage latch means
11
, and then entered to the second comparator COM
12
. The second comparator COM
12
compares the voltage (VREFINT: first input voltage ) determined by the reference voltage VREF with the voltage(VREGLEVEL: second input voltage) determined by the input voltage VPPI. If the second input voltage VREGLEVEL is higher than the first input voltage VREFINT, the second comparator COM
12
outputs high potential and lowers output voltage OUT by turning on a first NMOS transistor M
11
. While the second input voltage VREGLEVEL is lower than the first input voltage VREFINT, it outputs low potential and allows the input voltage VPPI to rise again by turning off the first NMOS transistor M
11
. Such a potential of the second input voltage VREFLEVEL of the second comparator COM
12
is determined by a diode chain
13
. Each PMOS transistor D
11
to D
1
n
of the diode chain
13
is controlled by each switch S
11
to S
1
n
in a switching means
12
. Also, the switching means
12
is controlled by a high voltage latch means
11
. The first through Nth high voltage latch circuits L
1
through LN of the high voltage latch means
11
are operated as a level shifter, respectively to latch the input voltage VPPI generated from the positive charge pump circuit
10
and then to output low voltage by each control signal C
1
to Cn. If the low voltage is outputted from a third high voltage latch circuit L
3
by the control signal C
3
, the switch S
13
is turned on, and thus the PMOS transistor D
13
does not operate. As the result, the input voltage VPPI passes through the switch S
13
without going through the PMOS transistor D
13
, and then is entered to a first node K
11
. Therefore, the output voltage VPPI of the positive charge pump circuit
10
is entered to a second node K
12
after being dropped as much as the threshold voltage of the remain transistors D
14
to D
1
n
. Since the second NMOS transistor N
10
is turned on but the third NMOS transistor N
11
is turned off by the enable signal EN, the voltage applied to the second node K
12
is entered to the second comparator COM
12
.
While such a multi-step pulse generating circuit uses each different number of PMOS transistors D
11
to D
1
n
to comprise a diode chain
13
determining the potential of a second input signal VREGLEVEL of the second comparator, the circuit may have desirable VPPI potential because the second input potential VREGLEVEL of the second comparator to have the potential dropped as much as the diode threshold voltage corresponding to the number of diodes changes. For the result, diodes are needed as many as the steps required by the first through Nth high voltage latch circuits L
1
to LN, the gate control circuit of PMOS transistors S
11
to S
1
n
that are the switches to turn on/off each PMOS transistors D
11
to D
1
n
of a diode chain
13
. On the process to drive each switch S
11
to S
1
n
, if the size of each transistor to comprise switches is not appropriate, coupling of parasitic capacitors occurs and circuit does not operated in normal since the junction of each transistor S
11
to S
1
n
and the n-well is jointly connected, and junction of the transistors S
11
to S
1
n
and that of each PMOS transistor D
11
to D
1
n
is also jointly connected. Also there is a problem in that inevitable delay occurs due to the serial feedback structure that output voltage VPPI of a positive charge pump circuit
10
is discharged after passing through a diode chain and then being compared in a second comparator COM
12
.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a multi-step pulse generating circuit for a flash memory to simplify circuit configuration and to reduce device area by fixing high voltage generated from a positive charge pump circuit and changing the potential of the compared reference voltage.
To achieve the above objects, a multi-step pulse generating circuit for a flash memory in accordance with the present invention comprising:
a reference voltage generating circuit to generate uniform voltage;
a first comparator to compare the output voltage of the reference voltage generating circuit with the feedback value;
a voltage drop means to get desirable voltage by dropping the output voltage of the first comparator; a positive charge pump circuit to generate desirable high voltage; a diode chain to drop the output voltage of the positive charge pump circuit; a second comparator to compare the output voltage of the voltage drop means and the output of the diode chain; and a switching means to control the output voltage of the positive charge pump circuit depending on the output of the second comparator.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
BRIEF DESCRIPTION OF THE DRAWINGS
The above object, and other features and advantages of the present invention will become more apparent by describing the preferred embodiment thereof with reference to the accompanying drawings, in which:
FIG. 1
is a conventional multi-step generating circuit for a flash memory;
FIG. 2A
is a multi-step pulse generating circuit for a flash memory in accordance with a first embodiment of the present invention;
FIG. 2B
is waveforms for explaining
FIG. 2A
;
FIG. 3A
is a multi-step pulse generating circuit for a flash memory in accordance with a second embodiment of the present invention; and
FIG. 3B
is a waveforms for explaining FIG.
3
A.
Similar reference characters refer to similar parts in the several views of the drawings.
REFERENCES:
patent: 5257225 (1993-10-01), Lee
patent: 5448712 (1995-09-01), Kynett et al.
patent: 5680350 (1997-10-01), Lee
patent: 5956272 (1999-09-01), Roohparvar
patent: 6097632 (2000-08-01), Roohparvar
patent: 7-073685 (1995-03-01), None
patent: 7-312093 (1995-11-01), None
patent: 8-036893 (1996-02-01), None
patent: 9-055092 (1997-02-01), None
patent: 10-228786 (1998-08-01), None
Hyundai Electronics Industries Co,. Ltd.
Lam David
Nelms David
Pennie & Edmonds LLP
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