Multi-step planarization process using polishing at two differen

Details Multi-step planarization process using polishing at two differen Multi-step planarization process using polishing at two differen

1995-11-24

1997-09-09

Breneman, R. Bruce

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

216 88, 216 2, 216 11, 438699, 438427, H01L 21306

Patent

active

056652020

ABSTRACT:
A process for polish planarizing a fill material (40) overlying a semiconductor substrate (30) includes a multi-step polishing process. In one embodiment, a second planarization layer (42) is deposited over a fill material (40) and a portion of the fill material (40) is removed leaving a remaining portion (44). The pad pressure of a CMP apparatus (20) is adjusted such that a first pressure is generated during the polishing process. Then, the remaining portion (44) is removed, while operating the CMP apparatus (20) at a second pad pressure. The selectivity of the polishing process is maintained by reducing the pad pressure during the second polishing step. In a second embodiment, after the first polishing step is performed, the remaining portion (44) is removed by an etching process using a portion (46) of second planarization layer (42).

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