Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-05-18
2002-05-21
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S691000, C438S692000
Reexamination Certificate
active
06391792
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods for forming patterned planarized aperture fill layers within apertures within topographic substrates employed microelectronic fabrications. More particularly, the present invention relates to methods for forming, with enhanced planarity and with attenuated topographic substrate erosion, patterned planarized aperture fill layers within apertures within topographic substrates employed within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly more common within the art of microelectronic fabrication, and particularly within the art of semiconductor integrated circuit microelectronic fabrication, to form within apertures within topographic substrates, and particularly within isolation trenches within topographic semiconductor substrates, patterned planarized aperture fill layers, and in particular patterned planarized trench isolation regions. In particular with respect to patterned planarized trench isolation regions, patterned planarized trench isolation regions method as are trenches within topographic semiconductor substrates within semiconductor integrated circuit microelectronic fabrications are desirable insofar as they provide semiconductor integrated circuit microelectronic fabrications which may be fabricated with enhanced functionality, enhanced reliability and enhanced yield.
While patterned planarized aperture fill layers, such as but not limited to patterned planarized trench isolation regions, are thus desirable in the art of microelectronic fabrication, patterned planarized aperture fill layers, such as but not limited to patterned planarized trench isolation regions, are not formed entirely without problems in the art of microelectronic fabrication. In particular, when forming within microelectronic fabrications patterned planarized aperture fill layers such as but not limited to patterned planarized trench isolation regions while employing conventional chemical mechanical polish (CMP) planarizing methods, such patterned planarized aperture fill layers are often formed with dishing within the patterned planarized aperture fill layers and/or with erosion of adjoining portions of a topographic substrate layer into which are formed the patterned planarized aperture fill layers.
It is thus towards the goal of forming within the art of microelectronic fabrication patterned planarized apertures fill layers, such as but not limited to patterned planarized trench isolation regions, with enhanced planarity and with attenuated topographic substrate erosion, that the present invention is directed.
Various methods for forming patterned planarized aperture fill layers within apertures within topographic substrates employed within microelectronic fabrications, and in particular patterned planarized shallow trench isolation (STI) regions within shallow isolation trenches within topographic semiconductor substrates employed within semiconductor integrated circuit microelectronic fabrications, have been disclosed within the art of microelectronic fabrication, and in particular in the art of semiconductor integrated circuit microelectronic fabrication.
For example, Zheng et al., in U.S. Pat. No. 5,728,621, disclose a method for forming, with enhanced planarity, within a shallow isolation trench formed within a topographic semiconductor substrate employed within a semiconductor integrated circuit microelectronic fabrication, a patterned planarized shallow trench isolation (STI) region formed employing a high density plasma chemical vapor deposition (HDP-CVD) method. To realize the foregoing result, the method employs a composite bilayer comprising a sacrificial spin-on-glass (SOG) planarizing layer formed upon a blanket high density plasma chemical vapor deposition (HDP-CVD) deposited dielectric layer in turn formed within the shallow isolation trench within the topographic semiconductor substrate, where the composite bilayer is first etched back while employing a blanket etchback method, and then chemical mechanical polish (CMP) planarized.
In addition, Varian et al., in U.S. Pat. No. 5,880,007 also disclose a method for forming, with enhanced planarity, within a shallow isolation trench formed within a topographic semiconductor substrate employed within a semiconductor integrated circuit microelectronic fabrication, a patterned planarized shallow trench isolation (STI) region formed employing a high density plasma chemical vapor deposition (HDP-CVD) method. To realize the foregoing result, the method employs formed upon a high density plasma chemical vapor deposition (HDP-CVD) deposited dielectric layer formed within the shallow isolation trench within the topographic semiconductor substrate a conformal sacrificial polish stop layer, in conjunction with a three step planarizing method which employs: (1) a first chemical mechanical polish (CMP) planarizing method, followed by; (2) a selective reactive ion etch (RIE) etchback method, in turn followed by; (2) a second chemical mechanical polish (CMP) planarizing method.
Further, Yu, in U.S. Pat. No. 5,911,110, discloses a method for forming, with enhanced planarity and with attenuated substrate damage, within a shallow isolation trench formed within a topographic semiconductor substrate employed within a semiconductor integrated circuit microelectronic fabrication, a patterned planarized shallow trench isolation (STI) region. To realize the foregoing result, the method employs: (1) a selective reactive ion etch (RIE) etchback of a blanket shallow isolation trench fill dielectric layer to form a patterned shallow isolation trench fill dielectric layer while employing a reverse tone mask which also incorporates therein a dummy pattern over a comparatively wide mesa portion of the topographic semiconductor substrate, followed by; (2) a chemical mechanical polish (CMP) planarizing of the patterned shallow isolation trench fill dielectric layer while employing a chemical mechanical polish (CMP) planarizing method.
Finally, Parekh et al., in U.S. Pat. No. 5,945,724, disclose a method for forming, with rounded corners, within a semiconductor substrate employed within a semiconductor integrated circuit microelectronic fabrication, a shallow isolation trench which thus provides when planarized within the shallow isolation trench a patterned planarized shallow trench isolation (STI) region also formed with rounded corners. To realize the foregoing result, the method employs when forming the shallow isolation trench with the rounded corners within the semiconductor substrate a sacrificial spacer layer formed within an aperture within a masking layer which is employed for defining the shallow isolation trench while employing a reactive ion etch (RIE) shallow isolation trench etch method.
Desirable in the art of microelectronic fabrication are additional methods and materials which may be employed for forming with enhanced planarity and with attenuated topographic substrate erosion within topographic substrates employed within microelectronic fabrications, such as but not limited to semiconductor integrated circuit microelectronic fabrications, patterned planarized apertures fill layers, such as but not limited to patterned planarized trench isolation regions, within apertures, such as but not limited to isolation trenches, within those topographic substrates within those microelectronic fabrications.
It is towards the foregoing object that the present invention is directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a method for forming within an aperture within a topographic substrate employed within a microelectronic fabrication a pattern
Chang Chung-Long
Cheng Juing-Yi
Jang Syun-Ming
Everhart Caridad
Taiwan Semiconductor Manufacturing Co. Ltd
Tung & Associates
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