Multi-state nonvolatile semiconductor memory device which is...

Details Multi-state nonvolatile semiconductor memory device which is... Multi-state nonvolatile semiconductor memory device which is...

2000-10-31

2002-06-25

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180

Reexamination Certificate

active

06411551

ABSTRACT:

This application relies from priority upon Korean Patent Application No. 1999-47959, filed on Nov. 1, 1999, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention is related to semiconductors memory devices, and more particularly to a nonvolatile semiconductor memory device, which stores information of plural bits per cell.
BACKGROUND OF THE INVENTION
Non-volatile integrated circuit memory devices can be classified into the following categories: mask ROMs; EPROMs; EEPROMs; and flash-EEPROMs. Among these memory devices, flash-EEPROMs have recently been discussed as permanent memories for personal computers in that they can achieve an electrical conversion of information while erasing stored data in a flash.
In conventional non-volatile memory devices, memory cells can take one of two information storing states, namely, the “ON” state and “OFF” state. One bit of information is defined by the ON or OFF state of a respective memory cell. In order to store data of N bits (N: a natural number of 2 or greater) in the conventional memory devices mentioned above, N independent memory cells are necessary. When it is required to increase the number of bits of data to be stored in a memory device having one-bit memory cells, the number of such memory cells should increase correspondingly.
Information stored in a conventional one-bit memory cell is determined by the programmed status of the memory cell where programming is used to store the desired information in the memory cell. The information storing state of the memory cell is determined by the threshold voltage which is a minimum voltage to be applied between the gate and source terminals of the transistor included in the memory cell in order to switch the cell transistor to its ON state. In other words, memory cells have different information storing states in accordance with different threshold voltages thereof. In the case of EPROMs, EEPROMs, and flash-EEPROMs, a difference in the threshold voltage for cell transistors is obtained by storing different amounts of charge in the floating gates of the memory cells.
In particular, each memory cell transistor has two gates including upper and lower layers laminated on a channel region between source and drain regions. The upper gate is called a control gate. A charge storage portion is surrounded by an insulating material between the control gate and the channel region. This charge storage portion is called a floating gate. Accordingly, the state of information stored in each memory cell can be distinguished by the threshold voltage of that memory cell.
In order to read information stored in the memory cells of a memory device, it is necessary to check the information storing state of the programmed memory cells. To this end, signals required to read state information from a selected memory cell are applied to circuits associated with the selected memory cell by use of a decoder circuit. As a result, a current or voltage signal indicative of the stored information of the memory cell can be obtained on a bit line. In this way, the programmed information of a memory cell can be found by measuring the obtained current or voltage signal.
These memory devices can have a NOR-type or a NAND-type memory cell array structure depending on the connection of the memory cells to respective bit lines. In a NOR-type memory cell array, each memory cell is connected between a bit line and a ground line. In a NAND-type memory cell array, a plurality of memory cells are connected in series between a bit line and a ground line. A group of memory cells connected in series to one bit line along with selection transistors used to select those memory cells is called a string. The selection transistors may include a first transistor (or a string select transistor) arranged between the series-connected memory cells and the associated bit line, and a second transistor (or a ground select transistor) arranged between the series-connected memory cells and a ground line.
When reading information stored in a NAND-type memory device, a selected transistor in a selected string is switched to the ON state. In addition, a voltage higher than that applied to the control gate of the selected memory cell is applied to the control gates of unselected memory cells. As a result, the unselected memory cells have a low equivalent resistance as compared to the selected memory cell. The magnitude of the current flowing through the string from the associated bit line thus depends on the information stored in the selected memory cell of the string. The voltage or current corresponding to the information stored in each selected memory cell is sensed by a sensing circuit which is generally known as a sense amplifier.
Many schemes have been proposed to increase the information storage capacity of memory devices without involving an increase in chip size. For example, information of at least two bits can be stored in each memory cell. Conventionally, a memory cell stores only one bit of information therein. However, when 2 bits of information are stored in one memory cell, this memory cell is programmed with either “00”, “01”, “10” or “11”. Accordingly, a memory device can store twice the information with the same number of memory cells as compared to a memory device wherein only one bit is stored in a memory cell. When storing 2 bits per memory cell, a multi-state memory device is provided wherein the threshold voltage of each memory cell can be programmed to have one of four different values. Because the memory capacity per memory cell is doubled, the chip size can be reduced while providing the same memory capacity. As the number of bits stored per memory cell increases, the data storage capacity of the multi-state memory device increases.
FIG. 1
is a circuit diagram showing a conventional memory device wherein two bits of information per memory cell are stored using a NAND-type flash-EEPROM cells. The memory device in
FIG. 1
is disclosed in U.S. Pat. No. 5,768,188 under the title of “MULTI-STATE NON-VOLATILE SEMICONDUCTOR MEMORY AND METHOD FOR DRIVING THE SAME”, which is herein incorporated by reference.
The memory device disclosed in the '188 patent includes two memory cell strings each having a plurality of series-connected memory cells. Two bit lines, associated with respective memory cell strings, are illustrated wherein these bit lines belong to different groups. As will be understood by one having skill in the art, larger numbers of memory cell strings and respective bit lines can be used. In
FIG. 1
, the memory cells of each string are labeled T
1
-
2
to T
1
-
5
or T
1
-
8
to T
1
-
11
, respectively. A selection transistor, T
1
-
1
or T
1
-
7
, is coupled between each string and the associated bit line. The selection transistor is selectively switched on to couple the associated string and bit line together. Another selection transistor, T
1
-
6
or T
1
-
12
, is arranged between each string and a common source line CSL to selectively switch the connection between the string and common source line CSL. A depletion transistor, D
1
-
1
or D
1
-
2
, is also coupled to each bit line to inhibit an application of high voltage.
A bit line selection transistor, S
1
-
1
or S
1
-
2
, is also connected to each bit line. Each bit line selection transistor selects a respective bit line in response to a bit line selection signal, A
9
or A
9
b
. A signal line BLLVL is connected to each of the bit lines via transmission transistors TM
1
-
1
and TM
1
-
2
. Each transmission transistor applies a signal BLLVL from the signal line BLLVL to the associated bit line in response to the bit line selection signals A
9
and A
9
b
applied thereto when the bit line is not selected. The signal BLLVL supplies a program inhibit voltage (for example, the supply voltage Vcc) to the unselected bit line during programming and reading operations while floating during the erase operation. A transistor T
1
-
13
is also connected to the bit lines to supply static current to the s

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