Multi-state logic analyzer integral to a microprocessor

Details Multi-state logic analyzer integral to a microprocessor Multi-state logic analyzer integral to a microprocessor

1999-11-04

2003-10-14

Teska, Kevin J. (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C703S028000, C714S039000, C714S739000

Reexamination Certificate

active

06633838

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to an on-chip logic circuit for debugging or analyzing microprocessor event trace data, and in particular to a multi-state on-chip logic analyzer having the capability count a programmable number of conditions before triggering and transitioning to the next state, and to store event trace data in an on-chip array for trace event reconstruction and analysis.
2. Description of the Related Art
VLSI circuits are becoming increasingly complex as the capability to construct more and more transistors, and thus logic elements, in smaller and smaller packages increases. As the complexity of VLSI circuits, such as, for example microprocessors and microcontrollers increases, the detection of internal circuit errors has become a priority. Consequently, several methods of testing and debugging VLSI circuits both at the wafer stage, and after component packaging have been implemented.
For example, external logic analyzers may be connected to the circuit under test to look for specific errors or sequences of events. These external logic analyzers are very proficient at capturing, storing, and analyzing microprocessor event trace data. Further, external logic analyzers can be programmed to trigger on specific error conditions, or to initiate specific events to examine VLSI circuit response. However, these external logic analyzers suffer from several problems. For example, external logic analyzers can be quite expensive. Further, because the sizes of VLSI circuits are continuously shrinking, simply connecting the external logic analyzer to the inputs and outputs of a VLSI circuit at the wafer stage, prior to component packaging, can be difficult. As a result, defective circuits may be packaged before an error that might render the circuit unusable can be detected. Further, because the external logic analyzer is by definition external to the VLSI circuit, capturing or monitoring of signals purely internal to the VLSI circuit may be difficult or impossible.
Other solutions, such as the use of oscilloscopes to measure electrical timing of the internal logic of VLSI circuits have also been implemented. Typically, oscilloscopes suffer from similar problems to those discussed for the external logic analyzers, namely expense, difficulty of connection at the wafer stage, and inability to monitor purely internal signals.
Still other solutions have used trace arrays within a VLSI circuit to capture event trace data. However, these circuits typically only have the ability to start or stop on a trigger event or condition. Consequently, such circuits are incapable of detecting multi-event error conditions. Further, such circuits do not have the ability to count events or to start or stop trace data capture at intermediate steps. Therefore, while such circuits are useful, their application is typically limited to testing for relatively simple error conditions.
Consequently, what is needed is a system and method for aiding in the debugging of VLSI circuits, at either the wafer or component stage, that does not require the use of external logic analyzers or oscilloscopes. This system should provide the capability to program multiple trigger events, and to initialize programmable conditions in desired states. Further, this system should provide the capability store event trace data for later reconstruction and analysis.
SUMMARY OF THE INVENTION
To overcome the limitations in the related art described above, and to overcome other limitations that will become apparent upon reading and understanding the present application, the present invention is embodied in a multi-state on-chip logic analyzer having the capability match one or more programmable trigger events to satisfy one or more programmable conditions, to initialize programmable conditions in desired states, and to store event trace data in an on-chip array for trace data reconstruction and analysis.
In general, the system and method of the present invention is embodied in a programmable multi-state logic analyzer integrated into a VLSI circuit. Further, the multi-state logic analyzer is coupled to a multilevel trace array for storing event trace data generated by the logic analyzer. Input and output logic coupled to both the trace array and the logic analyzer allows reading or writing from or to the trace array, and programming of condition or trigger criteria for transitioning states within the logic analyzer.
Specifically, the multi-state logic analyzer is preferably comprised of trace data control logic for generating triggers and controlling reads and writes to and from the trace array, and condition select logic for comparing conditions to programmable criteria to provide start, stop, run-n, stop-n, or reset commands to the trace data control logic. In other words, when a condition, or sequence of conditions, is either seen or met, writing to the trace array is preferably started, stopped, run for a programmable number of cycles, or stopped after a programmable number of cycles depending upon the programming of the condition select logic. Further, a reset command preferably allows the trace data control logic and the condition select logic to be reset to an initial state.
The trace data control logic preferably controls the running state of the trace array and generates triggers based on comparisons to programmable trigger criteria. The conditions that cause the condition select logic to transition from one state to the next are preferably programmable and are based on signals entering the trace data control logic from various logic units within the VLSI circuit to generate triggers. A plurality of programmable conditions are preferably met or enabled by one or more associated programmable trigger masks. Conditions are preferable met by a single trigger event.
Alternatively, in one embodiment, conditions are preferably met by counting a plurality of programmable trigger events to satisfy a single condition. In this embodiment, a bit-wise logical OR of the triggers for a given condition is preferably performed to form a trigger count input. When a trigger count matches a programmed trigger count value, the condition is preferably considered met. In other words, when one or more unique trigger events are seen a specified number of times, the condition is considered met.
In general, when a condition is considered met, either in the case of a single trigger condition, or where multiple triggers are used to define a condition, the condition select logic preferably transitions to a subsequent state, and either no command, or a start, stop, run-n, stop-n, or reset command is provided to the trace data control logic depending upon the programming of the condition select logic. Consequently, when a predefined condition is met, the trigger events causing the condition to be met are preferably written to the trace array, at which time, writing to the trace array continues, stops, runs for a programmable period, or stops after a programmable period depending upon the state and programming of the condition select logic.
Specifically, the condition select logic preferably begins in an initial state, however, the condition select logic is preferably programmable such that the condition select logic may begin in an intermediate state or condition. Writing of trigger event data to the trace array preferably begins with the first condition met, but may begin after any of the programmable conditions.
If after meeting one or more conditions, a subsequent condition is not met after a preferably programmable period of time, the condition select logic will preferably time out and transition back to an initial or intermediate condition at which time writing to the trace array is preferably stopped. However, if the subsequent condition is met, a final condition state is preferably entered for one cycle to generate a signal to the trace data control logic to complete writing of the trigger event data causing the final state to be entered.
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