Static information storage and retrieval – Floating gate – Multiple values
Patent
1997-12-29
1999-12-07
Nelms, David
Static information storage and retrieval
Floating gate
Multiple values
36518522, 36518511, 3651853, 36518533, 36518509, G11C 1604
Patent
active
059994460
ABSTRACT:
A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.
REFERENCES:
patent: 3895360 (1975-07-01), Cricchi et al.
patent: 3898632 (1975-08-01), Spencer, Jr.
patent: 3906455 (1975-09-01), Houston et al.
patent: 3914750 (1975-10-01), Hadden, Jr.
patent: 4005389 (1977-01-01), Penzel
patent: 4044339 (1977-08-01), Berg
patent: 4058799 (1977-11-01), George et al.
patent: 4064405 (1977-12-01), Cricchi et al.
patent: 4090258 (1978-05-01), Cricchi
patent: 4099069 (1978-07-01), Cricchi et al.
patent: 4115850 (1978-09-01), Houston et al.
patent: 4130890 (1978-12-01), Adam
patent: 4141081 (1979-02-01), Horne et al.
patent: 4193128 (1980-03-01), Brewer
patent: 4241424 (1980-12-01), Dickson et al.
patent: 4272830 (1981-06-01), Moench
patent: 4287570 (1981-09-01), Stark
patent: 4412309 (1983-10-01), Kuo
patent: 4428047 (1984-01-01), Hayn et al.
patent: 4433387 (1984-02-01), Dyer et al.
patent: 4449203 (1984-05-01), Adlhoch
patent: 4451905 (1984-05-01), Moyer
patent: 4460982 (1984-07-01), Gee et al.
patent: 4468729 (1984-08-01), Schwartz
patent: 4521852 (1985-06-01), Guttag
patent: 4521853 (1985-06-01), Guttag
patent: 4527257 (1985-07-01), Cricchi
patent: 4586163 (1986-04-01), Koike
patent: 4642798 (1987-02-01), Rao
patent: 4653023 (1987-03-01), Suzuki et al.
patent: 4685084 (1987-08-01), Canepa
patent: 4752871 (1988-06-01), Sparks et al.
patent: 4758986 (1988-07-01), Kuo
patent: 4758988 (1988-07-01), Kuo
patent: 4763305 (1988-08-01), Kuo
patent: 4780855 (1988-10-01), Irida et al.
patent: 4796235 (1989-01-01), Sparks et al.
patent: 4805151 (1989-02-01), Terada et al.
patent: 4811293 (1989-03-01), Knothe et al.
patent: 4811294 (1989-03-01), Kobayashi et al.
patent: 4821240 (1989-04-01), Nakamura et al.
patent: 4839705 (1989-06-01), Tigelaar et al.
patent: 4841482 (1989-06-01), Kreifels et al.
patent: 4847808 (1989-07-01), Kobatake
patent: 4860228 (1989-08-01), Carroll
patent: 4860261 (1989-08-01), Kreifels et al.
patent: 4860262 (1989-08-01), Chiu
patent: 4878203 (1989-10-01), Arakawa
patent: 4882642 (1989-11-01), Tayler et al.
patent: 4887234 (1989-12-01), Iijima
patent: 4920478 (1990-04-01), Furuya et al.
patent: 4931997 (1990-06-01), Mitsuishi et al.
patent: 4933906 (1990-06-01), Terada et al.
patent: 4939690 (1990-07-01), Momodomi et al.
patent: 4949309 (1990-08-01), Rao
patent: 4953129 (1990-08-01), Kobayashi et al.
patent: 4970692 (1990-11-01), Ali et al.
patent: 5033023 (1991-07-01), Hsia et al.
patent: 5036460 (1991-07-01), Takahira et al.
patent: 5043940 (1991-08-01), Harari
patent: 5053990 (1991-10-01), Kreifels et al.
patent: 5084843 (1992-01-01), Mitsuishi et al.
patent: 5095344 (1992-03-01), Harari
patent: 5095461 (1992-03-01), Miyakawa et al.
patent: 5163021 (1992-11-01), Mehrotra et al.
patent: 5168465 (1992-12-01), Harari
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5268870 (1993-12-01), Harari
patent: 5270979 (1993-12-01), Harari et al.
patent: 5270980 (1993-12-01), Pathak et al.
patent: 5274599 (1993-12-01), Ema
patent: 5297096 (1994-03-01), Terada et al.
patent: 5384743 (1995-01-01), Rouy
patent: 5388083 (1995-02-01), Assar et al.
patent: 5418752 (1995-05-01), Harari et al.
patent: 5434825 (1995-07-01), Harari
patent: 5619451 (1997-04-01), Costabello et al.
patent: 5719808 (1998-02-01), Harari
J.E. Brewer et al., "Block-Oriented Random Access MNOS Memory," National Computer Conference and Exposition, Chicago, May 6-10, 1974, AFIPS Conference Proceedings, vol. 43, pp. 837-840.
J.E. Brewer et al., "Low Cost MNOS BORAM,"Proceedings of IEEE National Aerospace Electronics Conference, NAECON '77, May 17-19, 1977, pp. 624-626.
J.R. Cricchi et al., "Nonvolatile Block-Oriented RAM," IEEE International Solid-State Circuits Conference, Feb. 13-15, 1974, Digest of Technical Papers, pp. 204-205.
Raul-Adrian Cernea et al., "A 1Mb Flash EEPROM," 1989 IEEE International Solid-State Circuits Conference.
Kenneth L. Short, "Microprocessors and Programmed Logic," second edition. "Ch. 13.2.2 Electrically Erasable Programmable Read Only Memory, EEPROM" Prentice Hall International, 1987, pp. 492-495.
Michael D. Fitzpatrick et al., "MNOS/SOS Memory Using High-Voltage Depletion-Mode CMOS Logic," pp. 196-199, Westinghouse Electric Corp., Baltimore, MD.
J.R. Cricchi et al., "The Drain-Source Protected MNOS Memory Device and Memory Endurance," IEDM Technical Digest, 1973, pp. 126-129.
Virgil Kynett et al., "An In-System, Reprogrammable 32K.times.8 CMOS Flash Memory," IEEE J. Solid-State Circuits, vol. 23, No. 5, Oct., 1988, pp. 1157-1163.
Denny Cormier, "Erasable/Programmable Solid-State Memories," EDN, pp. 145-154, Nov. 14, 1985.
Colin S. Bill, et al.; A Temperature-and Process-Tolerant 64K EEPROM, IEEE Journal of Solid State Circuits, vol. SC-20, No. 5, 1985, pp. 979-985.
Intel Corporation, 27F256 256K (32K.times.8) CMOS Flash Memory, Data Sheet, May 1988, pp. 1-21.
SEEQ Technology Incorp., 48F512 512K Flash EEPROM -- Preliminary Data Sheet, Oct. 1988, pp. 2-1 -2-24.
Wilson, "1-Mbit flash memories seek their role in system design," Computer Design, (Mar. 1, 1989) pp. 30 and 32.
Stark, M., "Two Bits Per Cell Rom," IEEE Catalog No. 81-CH1626-1, Library of Congress No. 80-85186, Order No. 341, Spring Comp Con 1981, Feb. 23-26, Twenty-Second Computer Society International Conference, San Francisco, CA, pp. 209-212.
Furuyama et al., "An Experimental 2-Bit/Cell Storage Dram For Macro Cell Or Memory-On-Logic Application," pp. 4.4.1 -4.4.4, IEEE, (1988).
Horiguchi et al., "An Experimental Large-Capacity Semiconductor File Memory Using 16-Levels Cell Storage," IEEE Journal Of Solid-State Circuits, vol. 23, No. 1 (Feb., 1988), pp. 27-33.
Krick, P.J., "Three-State MNOS Fet Memory Array, " IBM Technical Disclosure Bulletin, vol. 18, No. 12, pp. 4192-4193 (May, 1976).
Alberts, et al., "Multi-Bit Storage Fet EAROM Cell," IBM Technical Disclosure Bulletin, vol. 24, No. 7A, pp. 3311-3314 (Dec., 1981).
Bleiker et al., "A Four-State EEPROM Using Floating-Gate Memory Cells," IEEE Journal of Solid-State Circuits, vol. SC-22, No. 3 (Jun., 1987), pp. 460-463.
Nakayama et al. "A 60ns 16Mb Flash EEPROM With Program and Erase Sequence Controller". IEEE Journal of Solid-State Circuits, vol. 26, No. 11, Nov. 1991, New York US, pp. 1600-1605.
Harari Eliyahou
Mehrotra Sanjay
Norman Robert D.
Nelms David
SanDisk Corporation
Tran Andrew Q.
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