Multi-stage symbol synchronization

Details Multi-stage symbol synchronization Multi-stage symbol synchronization

1997-02-13

1998-06-09

Mis, David

Demodulators

Phase shift keying or quadrature amplitude demodulator

375355, 375324, H03D 300, H04L 2700, H04L 2722

Patent

active

057641021

ABSTRACT:
A digital communication receiver (#10) takes one complex sample (#20) of a baseband analog signal (#12) per symbol. A rectangular to polar converter (#44) separates phase attributes of the complex samples from magnitude attributes during coarse symbol synchronization (#28). A phase processor (#48) identifies clock adjustment opportunities which occur when relatively large phase changes take place between consecutive symbols. A magnitude processor (#46) influences symbol timing only during clock adjustment opportunities. The magnitude processor (#46) advances symbol timing in a phase locked loop when decreasing magnitude changes are detected during clock adjustment opportunities and retards symbol timing when increasing magnitude changes are detected during clock adjustment opportunities during coarse symbol synchronization (#28). A fine symbol synchronizer (#42) is used to refine coarse estimates of symbol synchronization in a data-directed manner (#82) by estimating incoming signal at sub-symbol intervals before and sampling instants to control oscillator (#22) in response to incoming signal estimates.

REFERENCES:
patent: 4215239 (1980-07-01), Gordy et al.
patent: 4652834 (1987-03-01), McAdam
patent: 5440265 (1995-08-01), Cochran et al.
patent: 5671257 (1997-09-01), Cochran et al.

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