Multi-stage serial-to-parallel/parallel-to-serial converter proc

Details Multi-stage serial-to-parallel/parallel-to-serial converter proc Multi-stage serial-to-parallel/parallel-to-serial converter proc

1990-10-22

1991-10-08

Williams, Howard L.

Coded data generation or conversion

Digital code to digital code converters

Serial to parallel

341101, 377 76, H03M 900

Patent

active

050558420

ABSTRACT:
A circuit for parallel-to-serial or serial-to-parallel conversion uses a multi-stage structure for conversion of long data words section-by-section. Each section of the data word corresponds to length/width of the respective registers or latches of the circuit which are successively controlled by an executive sequencer to process the data word in these smaller sections. The section-by-section conversion provides, for a high data rate, a reduction in clock loading and power dissipation.

REFERENCES:
patent: 4003083 (1977-01-01), Gariazzo
patent: 4274085 (1981-01-01), Marino, Jr.
patent: 4369504 (1983-01-01), Hanmura
patent: 4620180 (1986-10-01), Carlton
patent: 4799040 (1989-01-01), Yanagi
patent: 4901076 (1990-02-01), Askin et al.
"FIFO Registers with more I/O Make Better System Glue", Electronic Design, 35, Feb. 19, 1987, No. 4, Hasbrouck Hts., NJ, p. 40.
"Memory Based CMOS FIFO Buffers Sport Large Capacities, Rival the Speed of Bipolars", Technology Update, Electrical Design News, 32, No. 6, Newton, MA, Mar. 18, 1987, pp. 65-72.
"Modulares Optisches Ubertragungssystem fur Datenraten bis 200 MBit/s", Karl Schrodinger, 37 Elektronik, Sep. 16, 1988, No. 19, Munich, W. Germany, pp. 63-67.
Siemens Datenbuch Mikroprozessorbausteine, Edition 1976/77 (2 sheets).

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