Multi-stage ROM wherein a cell current of a selected memory cell

Details Multi-stage ROM wherein a cell current of a selected memory cell Multi-stage ROM wherein a cell current of a selected memory cell

1996-04-01

1997-09-16

Nelms, David C.

Static information storage and retrieval

Read only systems

Semiconductive

36518907, 36523006, G11C 1710

Patent

active

056687524

ABSTRACT:
For a nonvolatile multi-stage semiconductor memory device, a data reading sequence is given first, second, and third phases. During the first phase, a word line is driven to 2.25 V with a differential amplifier and a bias circuit activated to sense on or off of a selected memory cell. During the second phase, the word line is driven to 3.0 V with a differential amplifier and a bias circuit activated to sense on or off of the selected memory cell. This enables correct read out with a low operating voltage, such as 3.0 V, of data stored in semiconductor memory cells with a selected one of four threshold levels given to each datum. During the third phase, it is possible to use the differential amplifier and the bias circuit which are used during the first phase. Use of one differential amplifier alone is possible with two bias circuits used. Use of only first and second phases is also possible.

REFERENCES:
patent: 5323342 (1994-06-01), Wada et al.
patent: 5341337 (1994-08-01), Hotta

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