Multi-stage programmable Johnson counter

Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Pulse multiplication or division

Reexamination Certificate

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Details

C377S126000, C327S115000, C327S117000, C327S278000, C327S279000

Reexamination Certificate

active

06876717

ABSTRACT:
A counter has selectable divide factors using multiple multiplexers. The counter includes an inverter and cascading delay stages having selectable stage delays. The inverter connects a stage output of a last one of the delay stages to a stage input of a first one of the delay stages. Each delay stages includes a stage input to receive a quotient signal, at least two paths having different associated path delays each coupled to receive the quotient signal from the stage from the stage input, and a multiplexer. The multiplexer is coupled to selectively communicate the quotient signal from one of the at least two paths to a stage output to select one of the stage delays.

REFERENCES:
patent: 5420531 (1995-05-01), Wetlaufer
patent: 5898242 (1999-04-01), Peterson

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