Multi-stage pipeline architecture for motion estimation block ma

Details Multi-stage pipeline architecture for motion estimation block ma Multi-stage pipeline architecture for motion estimation block ma

1996-06-19

1997-07-29

Chin, Tommy P.

Television

Bandwidth reduction system

Data rate reduction

348699, H04N 732

Patent

active

056526253

ABSTRACT:
An apparatus for implementing motion estimation block matching for video image processing. The apparatus receives pixel data of original and compared image blocks for comparison, to obtain an image motion vector. The apparatus has a multi-stage pipelined tree-architecture that includes a computation stage, a summation section, an accumulation stage, and a minimum value evaluation stage. The computation stage includes 2.sup.n computation members for producing a difference error value and a sign bit of the compared image blocks. The summation section coupled at the pipelined stage next to the computation stage, includes a series of summation stages for producing an absolute error value of the compared image blocks. A following accumulation stage adds an output of the single adder means of the last summation stage and a last un-added sign bit, for producing a sum. A last minimum value evaluator evaluates and generates the minimum of the output of the accumulation stage, as the motion vector for the implementation of motion estimation block matching for video image processing. Only a single adder is required in each of the computation members to reduce both the complexity and the processing delay for increased performance.

REFERENCES:
patent: 5030953 (1991-07-01), Chiang
patent: 5512962 (1996-04-01), Homma

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