Multi stage oscillator phase alignment scheme

Details Multi stage oscillator phase alignment scheme Multi stage oscillator phase alignment scheme

1999-02-09

2001-07-10

Le, N. (Department: 2861)

Incremental printing of symbolic information

Light or beam marking apparatus or processes

Scan of light

C347S235000, C347S248000

Reexamination Certificate

active

06259467

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to the field of electrophotographic reproduction devices and, more specifically, to alignment of signals used in electrophotographic reproduction devices.
BACKGROUND
Electrophotographic reproduction devices (e.g., copiers and printers) use a charged photoconductor that is selectively discharged by the operation of a print or imaging station, to provide an electrostatic latent image on the photoconductor's surface. Selective discharging is performed using light to which the photoconductor is sensitive. One prior art system uses a scanning laser beam that is modulated as it is scanned across the surface of the photoconductor. The photoconductor is discharged in areas where the laser is turned on while the photoconductor remains charged in areas when the laser is turned off.
A visual image, corresponding to the latent image on the photoconductor, is then printed onto the surface of a substrate material (e.g., a sheet of paper). The printing is achieved by first applying charged toner to the photoconductor and then transferring the toner to the substrate surface. The toner is transferred by placing, on the back side of the substrate, a charge that is of opposite polarity to the charge on the toner. When the substrate is placed in contact with the photoconductor and is then subsequently removed, the toner is attracted to the substrate surface resulting in the transfer of the latent image.
In electrographic reproduction devices, the area on the photoconductor that is exposed to the laser is referred to as a picture element (PEL). One scan of the laser beam across the photoconductor forms a PEL row of the latent image. The first PEL must be aligned in order for the PEL row to come out in a straight line all the way across the photoconductor. In addition, the phase of the laser beam must be controlled during each scan pass across the photoconductor such that the PELs of the current scanned row will line up with the corresponding PELs of subsequently scanned rows. In this way, parallel PEL columns are formed resulting in a uniform image being displayed. Many factors contribute to the misalignment of PEL rows including improper initialization of the first PEL and beam speed.
One prior art system uses a beam detect diode in a photodetector to facilitate proper alignment of the PEL rows. The scanning laser beam is split and when the split beam is swept across the diode, a beam detect pulse is triggered. Each time the laser is scanned across the photoconductor, the pulse is triggered at the same location. An oscillator and a phase alignment block is then used to align the start of the PEL rows with the leading edge of the beam detect pulse. The oscillator signal frequency is set such that one cycle of the oscillator signal corresponds to the length of a PEL in a scan row.
One prior art system accomplishes this alignment using a phase lock loop (PLL) circuit. The beam detect pulse is input to the PLL and used to synchronize an internal oscillator. An output signal is generated that is aligned with the beam detect pulse. The PEL rows are then aligned using the output signal of the PLL. However, it can be difficult to precisely synchronize the oscillator signal with the beam detect pulse. Any phase offset variation between oscillator signal and the beam detect pulse results in what is known as jitter. One problem with such a system is that PLLs may allow for substantial jitter resulting in PEL alignment inaccuracies.
Another prior art system uses multi-tap delay lines to align the PEL rows with the beam detect pulse. In this type of system, an oscillator is used to generate a signal that is offset by a multi-tap delay block. A first delay tap receives the oscillator signal and delays it by a fixed amount (e.g., 1 to 2 nanoseconds) with each successive tap delaying the oscillator signal by an integer multiple of that fixed amount. The beam detect pulse is then compared against the delay taps to determine which one of the delay taps is nearest to the edge of the output signal. One problem with such a system is that it requires the use of multiple taps to obtain a fine resolution to completely span one full oscillator pulse. The fewer the number of taps that are used, the greater the resulting jitter. For example, if a PEL clock period is 30 nanoseconds (ns) and 10 taps (1 ns per tap) are used, then there would only be 10 positions within the 30 ns window from which to choose. As a result, approximately 3 ns of jitter may result in this example. In general, the delay spread completely covers the pel clock period.
SUMMARY OF THE INVENTION
The present invention provides a method for signal phase alignment that may include producing a pulse, producing a reference clock signal having a first frequency, generating an alignment clock signal, having the first frequency, aligned with the pulse, and realigning the first frequency of the alignment clock signal with the pulse.
In one embodiment, realigning the first frequency may include producing a plurality of delayed clock signals based on the reference clock signal, each of the plurality of delayed clock signals having one or more edges, latching the plurality of delayed clock signals based on the pulse, and selecting one of the plurality of delayed clock signals having an edge nearest to the pulse.
In another embodiment, the alignment clock signal may have one or more edges. The signal phase alignment method may further include adjusting the pulse based on the latched plurality of delayed clock signals, entering one of the edges of the alignment clock signal within the edges of the plurality of delayed clock signals, and selecting one of the plurality of delayed clock signals having an edge nearest to the adjusted pulse.
In another embodiment, the reference clock signal has one or more clock edges and the pulse has a pulse edge. Generating an alignment clock signal includes receiving the pulse; and aligning one of the clock edges of the reference clock signal with the pulse edge.
In yet another embodiment, the present invention provides a phase alignment circuit including a signal generator and a signal realignor. The signal generator and the signal realignor further include a pulse, a reference clock signal, a phase lock loop, a multi tap delay, and a latch bank. The phase locked loop may have a first input that may be coupled to receive the pulse, a second input that may be coupled to receive the reference clock signal and an output. The multi tap delay may have an input that may be coupled to the output of the phase locked loop and a plurality of outputs. The latch bank may have a plurality of inputs coupled to receive the pulse and a plurality of outputs.
In yet another embodiment, the phase alignment circuit may also include a combination logic and a control logic. The combination logic may be coupled to receive the plurality of outputs of the multi tap delay and may be coupled to receive the plurality of outputs of the latch bank. The combination logic may have a clock output and a range output. The control logic may be coupled to receive the range of output of the combination logic and may have an output to adjust the pulse received by the latch bank based on the range output of the combination logic.
Additional features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows.


REFERENCES:
patent: 5081477 (1992-01-01), Gibson
patent: 5438353 (1995-08-01), Morrison
patent: 5485195 (1996-01-01), Nacman
patent: 5606648 (1997-02-01), Walther et al.

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