Amplifiers – With periodic switching input-output
Reexamination Certificate
2001-08-15
2003-06-10
Tokar, Michael (Department: 2819)
Amplifiers
With periodic switching input-output
C330S051000, C330S133000, C330S258000, C330S292000, C341S155000, C341S161000, C341S162000, C341S163000
Reexamination Certificate
active
06577185
ABSTRACT:
BACKGROUND
This invention is related to operational amplifiers, and in particular to operational amplifiers to use as interstage amplifiers for analog-to-digital converters, in particular low-voltage low-power pipeline analog-to-digital converters.
Analog-to-digital converters (ADCs) with pipeline architecture are well suited for low-power, high-speed applications, for example for inclusion in integrated circuits such as CMOS integrated circuits. Advantages of the pipeline architecture over other architectures for high-speed applications include small die-area and low-complexity. CMOS technology is well established and offers the advantages of high levels of integration and low fabrication costs. CMOS can be used for both analog and digital functions, often on the same device.
Designing such pipeline ADCs for very low power and deep sub-micron CMOS digital processes is a challenge due mostly to reduced dynamic range and low supply voltage, e.g. 2.5V, while maintaining signal-to-noise ratio (SNR) and signal-to-noise and distortion ratio (SINAD). For example, with low supply voltage, the threshold voltages of the MOS devices used in analog circuits such as amplifiers used in a pipeline ADC can constrain the designs.
FIG. 1
shows a block diagram for a typical pipeline ADC
100
. While ADC
100
of
FIG. 1
is labeled prior art, a pipeline ADC conforming to the architecture of FIG.
1
and having one or more features of the invention described herein may not be prior art. Pipeline ADC
100
produces an N-bit number B
N−1
, . . . , B
1
, B
0
and comprises a number, say K, of stages, shown numbered (K−1), (K−2), . . . , 1, 0 in
FIG. 1
, with each stage responsible for resolving one or more bits. Each stage need not be identical. For example, each stage may be responsible for resolving a different number of bits. For simplicity, all stages but the last are assumed identical. Each stage produces a digital output and an analog residue output. The digital outputs of stages (K−1), (K−2), . . . , 1, 0 are respectively labeled P
K−1
, P
K−2
, . . . , P
1
, P
0
in
FIG. 1
The stages may all produce a digital output with the same number of bits, or a digital output with an unequal number of bits. The digital output P
K−1
, P
K−2
, . . . , P
1
, P
0
are input to a code converter to produce the N-bit output B
N−1
, . . . , B
1
, B
0
. The analog residue signal produced by each stage but the last is input to the next stage.
One example is a “1.5-bit” per stage converter. One bit is resolved at each stage, with the resulting analog residue passed along to the next stage for resolution of another bit. The digital output in such an example, the final stage might be a two-bit flash ADC that resolves the two least significant bits. In one example, such an architecture includes N−2 stages and one two bit ADC for the final stage for an N-bit converter. The code output by each stage may a three value output (e.g., a signal having value of −1, 0, or +1) or two binary output signals, called the full bit and half bit outputs.
FIG. 2
shows one architecture for an intermediate stage, say the M'th stage
200
of ADC
100
. While ADC
200
of
FIG. 1
is labeled prior art, a pipeline ADC conforming to the architecture of FIG.
2
and having the features of the invention described herein may not be prior art. ADC
200
includes a sample and hold (S/H) circuit
203
to sample the residue from the previous stage, an analog-to-digital converter (ADC)
205
that determines the digital code P
M
for this stage, a digital-to-analog converter (DAC)
207
that produces an analog equivalent of P
M
, denoted V
DAC
(M), and a summing interstage amplifier
209
that subtracts the analog equivalent V
DAC
(M) from the sampled previous-stage residue to produce the residue V
RES
(M) that is fed to the next stage. In general, summing interstage amplifier
209
also multiplies the difference by a factor of 2
J
, where J is the integer part of the number of bits resolved at each stage. For a 1.5 bit stage of an N-bit converter with a 2-bit flash converter as the last stage, J is 1, so that the interstage amplifier outputs
V
RES
(
M
)=2(
V
RES
(
M
)−
V
DAC
(
M
))
for M=N−1, . . . , 2.
The interstage amplifier
209
may be implemented by a switched capacitor circuit that includes a fully differential operational amplifier. One such switched capacitor circuit incorporates the sample and hold for the next stage, so that a separate sample and hold circuit
205
is not necessary except for the first stage.
For relatively high speed and low settling time operation, the operational amplifier needs to have a very high gain-bandwidth product. One mechanism for achieving high gain is a vertical gain enhancing technique such as cascading. Cascoding, however, is relatively unsuitable for low voltage operation because, for example, threshold voltages are a significant fraction of the process supply voltage for deep sub-micron technologies, and there is insufficient supply voltage for the additional voltage drop across the cascode transistor. Another alternative for the operational amplifier is a cascaded set of differential amplifiers.
There is therefore a need for a cascaded operational amplifier for use in stages of a pipeline ADC that achieves a relatively high speed, e.g., 80 megasamples per second (Ms/s), a relatively low settling time, and that has relatively low power consumption with a low supply voltage.
Such a low-power operational amplifier may have limited dynamic range. For example, the output voltage swing may be limited, and with a low supply voltage, the common mode voltage of the amplifier (called the “inherent” common mode voltage) may vary by a significant fraction of the supply voltage. One way to overcome this is by careful control of the inherent common mode voltage of each of the cascaded differential amplifiers.
FIG. 3A
shows a typical CMOS differential amplifier
300
with common mode control circuitry
305
. Common mode control circuitry
305
typically requires a common mode current source in a feedback configuration, which may require one or more operational amplifiers, and thus itself consumes power. There typically is one such common mode control for the operational amplifier that includes the cascade of differential amplifiers. See U.S. Pat. No. 4,918,399 to Devecchi, et al. entitled “COMMON MODE SENSING AND CONTROL IN BALANCED AMPLIFIER CHAINS” for an example of common mode control circuitry that controls the common mode voltage of a set of cascaded differential amplifiers.
An alternate CMOS differential amplifier
330
is shown in FIG.
3
B. Differential amplifier
330
includes its own local common mode feedback circuit in the form of resistive-averaged common mode feedback. Two equal sized resistors
333
of resistance R are placed between the two outputs and explicitly generate the inherent common mode voltage V
CM-AMP
at their connecting node
335
. The connecting node
335
is connected to the commonly connected gates of transistors M
1
and M
2
. The approximate gain of the differential amplifier is set by the product of the transconductance, g
m
, of transistor M
3
, and the parallel combination of the output impedance of M
1
, M
3
, and the resistor of value R. Thus, differential amplifiers with different R values have different gains.
The output voltage swing of amplifier
330
is limited to about two threshold voltages. There thus is a difficulty of using such resistive common mode feedback amplifiers in the operational amplifier of the stages of a pipeline ADC that has a low supply, voltage. In particular, the maximum and minimum output voltages of the differential amplifiers need to match the maximum and minimum references of the ADC to maximize the dynamic range.
There thus is a need for controlling the one or more reference voltages for the stages of a pipeline ADC relative to the inherent common mode voltages of the operational amplifiers in the stages. In particular, for operat
Allworth Peter C.
Chandler Rodney J.
Harrison Jeffrey N.
Cisco Systems Wireless Networking (Australia) Pty. Limited
Inventek
Khai Nguyen
Rosenfeld Dov
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