Multi-stage multiplexing chip set having switchable...

Details Multi-stage multiplexing chip set having switchable... Multi-stage multiplexing chip set having switchable...

2003-06-24

2008-10-28

Ngo, Ricky (Department: 2616)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

Reexamination Certificate

active

07443890

ABSTRACT:
A multi-stage bit stream multiplexer that divides multiplexing functions between two or more integrated circuits. The first integrated circuit receives 16 bit streams to produce 4 output bits streams with a nominal data rate of 10 GBPS. A second integrated circuit multiplexes the 4 streams and to a bit stream with a data rate of 40 GBPS. The first IC is made in a standard CMOS process while the second IC is made using processes that support higher switching rates. The first IC produces a source-centered double data rate forward transmit clock from a reference clock selectable from either a crystal oscillator, a voltage controlled oscillator using a loop clock from the receive side of the bit stream multiplexer or a reverse clock generated by the second IC. The reverse clock can be selected as the source of the reference either by default, or in response to a specific condition.

REFERENCES:
patent: 4360912 (1982-11-01), Metz et al.
patent: 4667324 (1987-05-01), Graves
patent: 4811341 (1989-03-01), Fujimoto et al.
patent: 5940456 (1999-08-01), Chen et al.
patent: 6657953 (2003-12-01), Hiramoto et al.
patent: 2003/0063626 (2003-04-01), Karlquist

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