Multi-stage integrated decoder device

Details Multi-stage integrated decoder device Multi-stage integrated decoder device

1988-03-16

1990-03-06

Shoop, Jr., William M.

Coded data generation or conversion

Digital code to digital code converters

Adaptive coding

341 56, 375 17, H03M 738

Patent

active

049069942

ABSTRACT:
A multi-stage integrated decoder device has a special function which facilitates the simultaneous activation of a plurality and as many as all of its outputs. When it is used as a bit line decoder it is thus possible to activate a plurality and as many as all of the bit lines (including any redundant bit lines) of a block of storage cells of a semiconductor memory.

REFERENCES:
patent: 3925780 (1975-12-01), Van Voorhis
patent: 4118791 (1978-10-01), Swain
patent: 4177455 (1979-12-01), Armstrong et al.
IEEE Journal of Solid-State Circuits, vol. SC-18, No. 5, Oct. 1983, pp. 457 to 462 "A 70 ns High Density 64K CMOS Dynamic RAM".
1986 IEEE International Solid State Circuits Conference, pp. 260-261 and 365; "A 47 ns 64KW.times.4b CMOS DRAM with Relaxed Timing Requirements".
The 10th International Symposium on Fault-Tolerant Computing; pp. 131-136; "FITPLA: A Programmable Logig Array for Function Independent Testing".
IBM Technical Disclosure Bulletin, vol 27, No. 4B, Sep. 1984; pp. 2439-2441; W. W. Proebster et al., "High-Speed Chip Card Reading".

Affiliated with

Also associated with

Rating

Multi-stage integrated decoder device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi-stage integrated decoder device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-stage integrated decoder device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-50171