Multi-stage dual successive approximation register...

Details Multi-stage dual successive approximation register... Multi-stage dual successive approximation register...

2011-07-12

2011-07-12

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000

Reexamination Certificate

active

07978117

ABSTRACT:
A multi-stage dual successive approximation register analog-to-digital converter (SAR ADC) and a method of performing analog-to-digital conversion using the same are provided. The multi-stage dual SAR ADC includes: a plurality of SAR ADC stages for converting an analog input voltage into a predetermined bit digital signal, each SAR ADC stage being serially connected to one another and including two SAR ADCs; and at least one residue amplifier respectively connected between every two successive SAR ADC stages, amplifying residue voltage output from a previous SAR ADC stage to output the amplified residue voltage to a next SAR ADC stage. The two SAR ADCs of the previous SAR ADC stage share the residue amplifier.

REFERENCES:
patent: 6124818 (2000-09-01), Thomas et al.
patent: 6879277 (2005-04-01), Cai
patent: 10-1997-0013785 (1997-03-01), None
Simone M. Louwsma et al., “A 1.35 GS/s, 10b, 175 mW Time-Interleaved AD Converter in 0.13μm CMOS,” Symposium on VLSI Circuits Digest of Technical Papers, pp. 62-63, 2007.

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