Electrical transmission or interconnection systems – Capacitor
Reexamination Certificate
1999-02-04
2001-02-06
Paladini, Albert W. (Department: 2836)
Electrical transmission or interconnection systems
Capacitor
C307S110000, C307S402000, C363S060000
Reexamination Certificate
active
06184594
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a charge pump circuit for generating a voltage on an integrated circuit device. More specifically, the present invention relates to a multistage charge pump having high-voltage pump control feedback.
BACKGROUND OF THE INVENTION
FIG. 1
is a circuit diagram of a conventional charge pump
10
used to generate a voltage on an integrated circuit chip. Charge pump
10
makes use of capacitors
1
-
8
, which are coupled to diodes
11
-
19
as illustrated. Capacitors
1
,
3
,
5
, and
7
are coupled in parallel to receive clock signal CLK, and capacitors
2
,
4
,
6
and
8
are coupled in parallel to receive clock signal CLK#. Clock signal CLK# is the inverse of clock signal CLK.
An input voltage V
IN
is provided to diode
11
and an output voltage V
OUT
is generated at the output terminal of diode
19
. Charge Pump
10
operates by pumping charge along diodes
11
-
19
as the capacitors
1
-
8
are successively charged and discharged during each half clock cycle. The voltages at nodes
21
-
28
are not reset after each pumping cycle. Consequently, the average potential of nodes
21
-
28
progressively increases from node
21
to node
28
.
Charge pump
10
has several disadvantages. First, each of diodes
11
-
19
experiences a series voltage drop. The sum of these voltage drops limits the voltage generated at the output terminal of diode
19
. Thus, many stages are required to generate a high voltage. In addition, it takes many clock cycles to charge capacitors
1
-
8
to provide the desired output voltage level. This latency exists because charge pump
10
sequentially charges one capacitor at a time, beginning with capacitor
1
and ending with capacitor
8
. The output terminal of diode
19
does not reach the desired voltage until capacitor
8
is charged.
Other conventional charge pumps charge a plurality of capacitors in parallel during a first cycle, and then discharge in the capacitors in series during a second cycle, thereby generating a relatively large voltage. Such a charge pump is described in U.S. Pat. No. 5,543,668. However, each stage of this charge pump only increases the output voltage by about V
CC
. It therefore requires a relatively large number of stages to generate an output voltage that is significantly greater than the input voltage. For example, this charge pump would require at least five stages to generate an output voltage of 16 Volts.
It would therefore be desirable to have a charge pump that generates a high output voltage in a relatively small number of stages. It would also be desirable if such a charge pump is able to provide the high output voltage in a relatively small number of clock cycles.
SUMMARY
Accordingly, the present invention provides a multistage charge pump that virtually doubles the input voltage in every stage, less pass transistor voltage drops. In a particular circuit, an input voltage of about 2.7 Volts is translated to an output voltage having a peak of about 19.55 Volts in three charge pump stages. The charge pump provides a peak output voltage of 16 Volts about 3 clock cycles after the charge pump is enabled. After about 8 clock cycles, the charge pump provides a peak output voltage of about 19.55 Volts.
In one embodiment, the charge pump comprises three stages. The first stage, which operates in response to a V
DD
supply voltage and a clock signal, alternately charges and discharges a pair of capacitors to generate a pair of first output voltages. Each of the first output voltages has a peak voltage which is approximately twice the V
DD
supply voltage. More specifically, in a particular embodiment, each of the first output voltages has a peak voltage equal to two times the V
DD
supply voltage minus the voltage drop of a pass transistor. If the V
DD
supply voltage is equal to 2.7 Volts and the pass transistor voltage drop is 0.15 Volts, then the first output voltages have a peak voltage of 5.25 Volts (i.e., (2×2.7 Volts)−0.15 Volts). The first output voltages are provided to control a second stage.
The second stage alternately charges and discharges a pair of capacitors in response to the first output voltages, thereby generating a pair of second output voltages. Each of the second output voltages has a peak voltage which is approximately two times the peak of the first output voltages. In a particular embodiment, the second output voltage has a peak voltage equal to four times the V
DD
supply voltage minus three times the pass transistor voltage drop (e.g., 10.35 Volts, or (4×2.7 Volts)−(3×0.15 Volts)). The second output voltages can be fed back to the second stage to bias a pair of pass transistors that are enabled to charge the pair of capacitors in the second stage. Providing the relatively high second output voltages to bias these pass transistors advantageously enables the capacitors in the second stage to be charged to a high voltage.
The third stage alternately charges and discharges a pair of capacitors in response to the second output voltages, thereby generating a pair of third output voltages. Each of the third output voltages has a peak voltage which is approximately two times the peak of the second output voltages. In a particular embodiment, the third output voltage has a peak voltage equal to eight times the V
DD
supply voltage minus seven times the pass transistor voltage drop and one diode voltage drop (e.g., 19.55 Volts, or (8×2.7 Volts)−(7×0.15 Volts)−1.0 Volt). The third output voltages can be fed back within the third stage to bias a pair of pass transistors that are enabled to charge the pair of capacitors in the third stage. Providing the relatively high third output voltages to bias these pass transistors advantageously enables the capacitors in the third stage to be charged to a high voltage.
In other embodiments, the present invention can include more than three stages. Each successive stage receives the output voltages provided by a previous stage, and in response, generates output voltages that are approximately twice as large. As indicated above, some voltage drop is experienced as the output voltages are transmitted from stage to stage through pass transistors. The output voltages provided by various stages can be fed back to control the charging of the capacitors within the stages.
The present invention will be more fully understood in view of the following description and drawings.
REFERENCES:
patent: 5051882 (1991-09-01), Grimm et al.
patent: 5057707 (1991-10-01), Pigott
patent: 5436587 (1995-07-01), Cernea
patent: 5543668 (1996-08-01), Fong
patent: 5623222 (1997-04-01), Tamagawa
patent: 5717581 (1998-02-01), Canclini
Bever Hoffman & Harms LLP
Hoffman E. Eric
Paladini Albert W.
Tower Semiconductor Ltd.
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