Multi-stage ADC with shared amplifier and reference voltage...

Details Multi-stage ADC with shared amplifier and reference voltage... Multi-stage ADC with shared amplifier and reference voltage...

2006-04-04

2006-04-04

Williams, Howard L. (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S161000

Reexamination Certificate

active

07023373

ABSTRACT:
The invention provides a clocked analog/digital converter for successive approximation which is designed using a jointly used amplifier and a dynamic range expansion facility by means of a special design for the comparison circuit in the first converter stage. The comparison circuits in the analog/digital converter allow decisions to be made for the further signal processing previously in a preceding time period. Two respective generator circuits in successive converter stages share one amplifier. This reduces the amount of space taken up and current drawn, increases the clock rate and simplifies signal processing for signals with high levels.

REFERENCES:
patent: 5764176 (1998-06-01), Ginetti
patent: 5835049 (1998-11-01), Nagaraj
patent: 5861832 (1999-01-01), Nagaraj
patent: 6809677 (2004-10-01), Konno
patent: 2005/0116846 (2005-06-01), Bogner
“A 250-mW, 8-b, 52-Msamples/s Parallel-Pipelined A/D Converter with Reduced Number of Amplifiers”, Krishnaswamy Nagaraj, H. Scott Fetterman, Joseph Anidjar, Stephen H. Lewis, and Robert G. Renninger, IEEE Journal of Solid-State Circuits, vol. 32, No. 3, Mar., 1997,pp. 312-320.
“A 69mW 10b 80-MS/s Pipelined CMOS ADC”, Byung-Moo Min, Peter Kim, David Boisvert and Arlo Aude, IEEE International Solid-State Circuits Conference 2003, 4 pp, no month.
“A 240-Mbps, 1-W CMOS EPRML Read-Channel LSI Chip Using an Interleaved Subranging Pipeline A/D Converter”, Tatsuji Matsuura, Takashi Nara, Tatsuya Komatsu, Eiki Imaizumi, Toshihiro Matsutsuru, Ryutaro Horita, Haruto Katsu, Shintaro Suzumura and Kzauo Sato, IEEE Journal of Solid-State Circuits, vol. 33, No. 11, Nov. 1998, pp. 1840-1850.
“Fir Switched-Capacitor Decimator Circuits with Time-Shared Amplifiers”, J.E. Franca and V.F. Dias, 30thMidwest Symposium on Circuits and Systems, 1988, pp. 1185-1188, no month.
“Systematic Method for the Design of Multiamplifier Switched-Capacitor FIR Decimator Circuits”, J. E. Franca, PhD and V. F. Dias, IEEE Proceedings-G, vol. 138, No. 3, Jun., 1991, pp. 307-314.
“Halbleiterschaltungstechnik”, U. Tietze and Ch. Schenk, Springer Publishing, 2002, pp. 1009-1011, no month.

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