Multi-speed retainer

Details Multi-speed retainer Multi-speed retainer

1997-11-10

2000-08-01

Patel, Ajit

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via frequency channels

370463, H04J 110

Patent

active

060977388

ABSTRACT:
A circuit and method comprising a first logic circuit, a second logic circuit and a speed detect circuit. The first logic circuit may be configured to present a global signal in response to a plurality of first speed indication signals. The speed detect circuit may be configured to present a plurality of second speed indication signals in response to an input operating at one of a plurality of speeds. The second logic circuit may be configured to present a plurality of internal speed indication signals, each in response to (i) the global signal and (ii) one of the plurality of the speed indication signals.

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S. Babar Raza et al., U.S.S.N. 08/970,059 Architecture for a Dual Segment Dual Speed Repeater, filed Nov. 13, 1997.
S. Babar Raza et al., U.S.S.N. 08/970,058 Architecture for a Dual Segment Dual Speed Repeater, filed Nov. 13, 1997.
M. Magdy Talaat et al., U.S.S.N. 08/976,410 Distributed Port Select Method for a Multi-Segment Repeater, filed Nov. 21, 1997.

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