Multi-speed logic analyzer

Details Multi-speed logic analyzer Multi-speed logic analyzer

1981-06-08

1984-01-10

Atkinson, Charles E.

Excavating

324 73R, 340721, 340801, 340802, G09G 108, G01R 3128

Patent

active

044256434

ABSTRACT:
A logic analyzer which can simultaneously measure one block of input data in detail and the same or another block of input data in rough form is disclosed. The logic analyzer comprises first and second sections each including a memory circuit to store the input data and a word recognizer to detect the desired trigger word from the input data. These first and second sections receive different clocks having different rates, and the second memory circuit stores the first clock applied to said first section for recognizing the time relationship of these clock signals. A counter counts the first clock in accordance with the outputs from the first and second word recognizers for recognizing the time relationship of the first and second trigger words.

REFERENCES:
patent: 3522597 (1970-08-01), Murphy
patent: 4139903 (1979-02-01), Morrill, Jr. et al.
patent: 4204114 (1980-05-01), Shoemaker et al.
patent: 4257043 (1981-03-01), Tsuchiko
patent: 4308615 (1981-12-01), Koegil et al.
patent: 4354260 (1982-10-01), Planzo
patent: 4364036 (1982-12-01), Shimizu
Farnbach, Logic State Analyzers-A New Instrument for Analyzing Sequential Digital Processes, IEEE Transactions on Instrumentation and Measurement, vol. IM-24, No. 4, Dec. 1975, pp. 353-356.

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