Multi-source video synchronization

Television – Synchronization – Locking of video or audio to reference timebase

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Details

348514, 348571, 348584, H04N 5073

Patent

active

055172539

DESCRIPTION:

BRIEF SUMMARY
The invention relates to multi-source video synchronization.


BACKGROUND OF THE INVENTION

1. Field of the Invention
Several unrelated video signals cannot be processed correctly in a single video effects system or displayed on a monitor, without being synchronized first. Namely, each video signal contains line and field synchronization pulses, which are converted to horizontal and vertical deflection signals for a monitor on which the video signal is displayed. The major problem is that the line and field synchronization pulses contained in the different video signals do not occur at the same time. If one of the video signals is used as reference signal, that is the horizontal and vertical deflection signals for a display are derived from this signal, then the following artifacts may appear: subsignals) will be shifted spatially on the display with regard to the reference signal. rise to visual artifacts like jagged edges and line flicker. reference video signal, then the images represented by these subsignals will crawl across the screen. parts of the same displayed image originate from different field/frame periods, which can be rather annoying in moving images where some parts of moving objects seem to lag behind.
2. Description of the Related Art
Traditionally, video synchronizers are built with frame stores that are capable to delay video signals from a few samples to a number of video frame periods. One of these video signals is selected as a reference signal and is not delayed. All samples of the other signals are written into frame stores (one store per signal) as soon as the start of a new frame is detected in these signals. When the start of a new frame in the reference video signal is detected, the read-out of the frame memory is initiated. This way, the vertical synchronization signals contained in the reference and other video signals appear at the same time at the outputs of the synchronization module.
FIG. 1 illustrates synchronization of a video signal with a reference video signal using a FIFO. FIG. 1 shows two independent video signals with their vertical (field) synchronization pulses FP, and the location of read and write pointers in a First-In-First-Out (FIFO) frame store. When a complete frame store is used, all the artifacts mentioned above can be eliminated. At instants SW (at the end of the subsignal (SS) field synchronization pulses FP), writing the subsignal samples a,b,c,d,e,f,g into the FIFO starts. At instants SR (at the end of the synchronization pulses FP of the reference signal RS), reading of the delayed subsignal samples a,b,c,d,e,f,g from the FIFO starts.
It is also possible to use a single field synchronization memory, i.e., the synchronization memory is reduced to one field per input source. In this case, all the above mentioned artifacts are prevented by performing a so-called field inversion, in case video is in the opposite field-phase of the field-phase being displayed on a monitor. This means that an incoming odd field can be locked to the even field that is currently being displayed (being read-out of the field memory) and the even field is locked to the odd field being displayed. To prevent interlace disorder in this case, a field dependent line-delay is applied. See U.S. Pat. Nos. 4,249,198; 4,797,743; and 4,766,506.
FIG. 2 illustrates locking fields of a video input signal to opposite fields of reference, by selectively delaying one field of input signal by one fine, whereby delay is implemented by delaying the read-out of the FIFO. The locking is shown for the case that the read address of the FIFO is manipulated: the displayed image is shifted down by one line. It is also possible to achieve this by manipulating the write address: a line delay in the write will cause upward shifting of the displayed image by one line. The left-hand part of FIG. 2 shows the reference video signal RS, the right-hand part of FIG. 2 shows the video subsignal SS. In each part, the frame line numbers are shown at the left side. The lines 1,3,5,7,9 are in odd fields, while the li

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"Low-cost Display Memory Architectures for Full-motion Video and Graphics", A. A. J. de Lange and G. D. La Hei, IS&T/SPIE High-Speed Networking and Multimedia Computing Conference, San Jose, USA, Feb. 6-10, 1994.

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